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DIDS-402-2AM13
The cursor, which is attached to the LSB of one character in memory,
is shifted into the CE register from 0 to 16 ms later.
When the character con-
taining the cursor is shifted into the CE register, a high is applied to cursor-
located flip-flop A 77.8 during CTS.
On the rising edge of 3CTS, A 77.8 is set to
pr oduce a high input at A18. 8.
This high enable s A5 7. 6 and during 3 C TS a cle ar
pulse is gated through the gate to clear the CE register.
Thus, if a character
code is associated with the cursor, the code is cleared before entering a new
character from the keyboard.
This accounts for the destructive effect of
positioning the cursor over a character and then depressing a character key •
. One phase time after clearing the CE register, AND-gate A53. 12 is enabled
and a write pulse is produced.
This pulse is applied to the second input of each
strobe gate; its purpose is to jam the 7-bit character code into the CE register.
When the INTERLK pulse reset A33. 6, it simultaneously enabled the
step-right flip-flop.
The step-right function is initiated as soon as the cursor is
located in the CE register (see paragraph 4-22.3.2).
Consequently, three
separate actions occur almost simultaneously: (1) clear CE register, (2) strobe
digital code into CE register, and (3) step the cursor right one character position.
4-23.1.3 Data from Buffer Register D3
In
the receive mode, data is coupled from buffer register D3 and enters
the CE register at the input to A56. 5.
From the previous discussion of SDL,
data is permitted to
~nter
the CE register only at the cursor position; therefore,
the cursor must be located (by SDL) before a serial transfer can occur.
This
is accomplished by monitoring the set output of A56. 5.
Data in the memory loop is circulated through the CE register in the
manner previously described.
Once per frame during the time corresponding
to the visible cursor on the screen, the output of A56. 5 goes high and remains
high during the interval 2CTS through 2(CTS+1).
The SDL circuitry senses this
level and during 3(CTS+1) the SDL flip-flop is set.
As previously stated, SDL
enables clock pulses for shifting the character out of D3.
The phase 2 register
clock (which is always present) then shifts the received character into the CE
register.
The cursor is automatically stepped right one character position by
a CR Q pulse developed by the SDL circuitry.
4-23. 1. 4 Data to Buffer Register Dl
In the transmit mode, data is extracted from memory beginning at the
cursor position and terminating at the first ETX character.
Before transmitting data, the memory is accessed in search of an ETX
code.
If an ETX has been inserted into memory by the operator, ETX decode
A58.8 is enabled Once per frame.
The decoded output is used to develop an
ETXSR pulse which is used to enable the transmit sequence.
Once the transmit
enable circuitry is enabled, data is extracted from memory by SDL each time the
cursor is shifted into the CE register.
Note that this transfer occurs by serially
shifting data out of the MSB position of the CE register (A56.5).
Each time SDL
goes high to extract a character, a CRQ pulse is developed to automatically step
the cursor right one character position.
In this manner, one and sometimes two
characters can be extracted sequentially, depending upon the status of the buffer
registers.
4-100
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