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DIDS-402-2AM13
4-24.2 Minor Vertical Sweep
The minor vertical sweep circuit is illustrated in figure 4-53. The 1.3 MHz-
minor ve rtical sweep signal, develope d by divide - by-two flip- flop A26. 12, is
used to produce high-resolution characters 0.13 inch high on the CRT.
The minor
vertical sweep circuit operates in the following manner.
Due to the design of
T2L logic elements, when neither the
J
nor K inputs of A26. 12 and A19. 12 are
connected to an external source, both inputs appear high.
Consequently, the
output complements on the trailing edge of each master clock or vertical drive
signal.
(The vertical drive input to A43. 3 is a negative going pulse that occurs
once per frame during vertical retrace. )
The output of each flip-flop is connected so that the
1.
3-MHz minor vertical
sweep un de
1
goes a lBO-degree phase shift at the beginning of each new frame.
Thus, on the 'first' frame, NAND-gate AlB.
6
is enabled and a 1. 3-MHz output is
produced.
At the end of vertical retrace, A19. 13 goes high and for the 'second'
frame AlB.
B
produces 1. 3-MHz clock outputs.
The reason for this phase shift is illustrated by the circuits that use the
minor vertical sweep signal.
In the monoscope deflection amplifier, the minor
vertical sweep signal is converted to a sine wave and applied simultaneously to
the diddle coil and the Y-axis deflection amplifier.
At the diddle coil, the
minor vertical signal 'modulate s' the horizontal deflection voltage, creating an
increased line height.
By reversing the phase on alternate frames, the frequency
of this modulating signal is effectively doubled and a sharper horizontal line
developed.
In the Y-axis amplifier, the minor vertical sweep signal cause s the
monoscope beam to 'paint' up and down over the character being scanned.
Again,
a phase reversal on alternate frames doubles the number of times the character
symbol is 'painted', and the resulting video signal more accurately defines the
character being scanned.
r-
J -:----. 12
MASTER
CLOCK .... _ _
......j
A26
K
J
AI9
K
D'DS 68-655
13
R65
3
I. 3M-Hz MINOR
~
IOOJ'l..
VERTICAL
12
13
Figure 4-53.
Minor Vertical Sweep,
Logic Diagram
4-24.3 Phase Counter
The phase counter (figure 4-54) is a divide-by-four counter which produces
four phase s of the master oscillator clock.
There is no provision for pre setting
the phase counter; therefore, during initial turn-on, anyone of the four decodes
may be enabled.
The first
1i2
pulse is used as a reference point to toggle the bit
4-137
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