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DIDS-402-2AMI3
When an STX character is received from the CPU, the STX flip-flop is set.
If the next character received is the correct DA, the ADDR flip-flop is set.
If
the address character has a 'I' in the MSB position, the STX flip-flop is reset
to produce conditions ADDR and STX.
These outputs are coupled to AND-gate
A81. 6 to enable one input of NAND-gate A72. 8.
The remaining inputs to A72. 8
are satisfied during the next character time when ETX is shifted into Dl.
The
ETX decode is enabled and ETXDI resets the STX and ADDR flip-flops while
ETXDI is used to enable the second input to A72. 8.
If ETX is received without
a parity error, the remaining inputs of A72. 8 are enabled during the ETX charac-
ter parity count.
The output of A 72.8 is inverted and combined with the reset
outputs of A 78.3 and A62. 8 to enable NAND-gate A63. 8.
The output of A63. 8 disables the R steering logic and raises the request-to-
send line; and Initialize Transmit clears buffer registers D2 and D3.
When the CS
reply is returned from the modem or CPU, AND-gate A54. 12 is enabled and, on
the next
Fa~H
pulse, Enter Header jams STX into D3, DA into D2, and ETX into
Dl, and enables the second input to A64. 8.
Approximately 16 ms later, Fa03
sets flip-flop A 70.11 to enable the T steering logic.
At this point, the delay-line memory is examined to determine whether an
ETX code has been inserted by the operator.
Keep in mind that presently STX
is in D3, DA is in D2 and ETX is in Dl.
If within 16 ms an ETX is not found in
the delay line (indicating that the operator has no message available), the next
Fa04 resets flip-flop A 78.3 and disables the input to A64. 8.
This prevents
destruction of the ETX code in Dl and the 'no-business' re sponse is transmitted
to the CPU.
When Enter Header jammed the STX, DA, and ETX character into
the buffer registers, flip-flop Ala. 8 was also set.
When the last character of
the 'no-business' response is transmitted, the transmit time-out flip-flop is set
to enable a return of the receive mode.
If an ETX code is found in memory, a message available condition is
indicated.
When the ETX character is shifted into the character entry register
the ETXSR output pulse is inverted and enables the third input of NAND-gate
A64.8.
The output of A64. 8 clears BBI (the busy bit for buffer register Dl)
thus allowing the first text character from n'1emory to be 'shifted into the register
'on top of' the ETX character received from the CPU.
In addition, the output pulse
is applied to cross-connected flip-flop gates A 73.6, A50.12, and A 72.6 to prevent
a recurrence of CLEAR BBI the next time the ETX code appears in the character
entry register.
The transfer of data from memory continues until the ETX character is
shifted into buffer register DI.
The ETXDI decoded output enables NAND-gate
A59.8
to set flip-flop Ala. 8.
When ETX is finally shifted out of buffer register
D3, gate A81. 12 enables NAND-gate A26. 6 and the transmit time-out function
is initiated.
4-22. 1. 3 Optional Operation
4-22. 1. 3. 1 Request-to-Send and Clear-to-Send
In some system.s, the Display Terminal is connected directly to the CPU,
and the RS and CS lines and the attendent time delay is not required.
As already
stated, it is not necessary for T2L integrated circuits to have every input connected
4-59
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