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DIDS-402-2AMI3
4-22.3.2 Transznit
In the transznit znode, the transznitted data line (BA) is held high by the STP
output of the deciznal counter.
When the de ciznal counter is released by f/JA gate
(or cycles frozn STP to STT as it finishes one count and begins another), the
start bit (a SPACE) is placed on the transznitted data line . . Siznultaneously, since
the deciznal counter is producing an STT output, the parity error flip-flop is
jaznzned reset.
On the next count of the deciznal counter, a high is produced at the output
of A53.
6.
This high perznits the first data bit of the character to pass frozn
buffer register D3 into the parity check flip-flop and on to the transznitted data
line.
During the next six bit tiznes, the reznaining bits of the character are
transznitted, while the nuznber of lis in the character are counted by the parity
check flip-flop.
If the transznitted character contains an odd nuznber of lis after seven bit
tizne s the parity check flip-flop is set.
During the next bit tizne, the deciznal
counter steps to its ninth count (PAR) and NAND-gate A5S. 6 is enabled.
This
places a 'I' on the transznitted data line to provide the correct parity.
If the transznitted character contains an even nuznber of lis after seven bit
tiznes the parity check flip-flop is reset.
When the deciznal counter steps to
PAR, NAND-gate ASS. 6 is not enabled.
This, in turn, places a '0' on the trans-
znitted data line in
th~
parity bit position of the character.
The tenth bit of the transznitted character is produced when the deciznal
counter steps to the next count.
The STP output is applied to NOR-gate A37. 8
to produce the stop bit (a MARK).
4-22.4 Buffer Register Control Logic
The purpose of the buffer register control logic is to control the znoveznent
of data through buffer registers Dl,
D2~
and D3.
The. control logic consists
of three busy-bit flip-flops (BBI, BB2, and BB3), and three shift control
flip- flops [ shift gate one-to-two (SGI2), shift gate two-to-three (SG23), and
shift to and frozn the delay line (SDL)].
The control logic circuitry is
shown in figures 4-28 and 4-29.
4-22.4. 1 Busy-Bit Flip-Flops
Each of the three busy-bit flip-flops is associated with a buffer register.
The purpose of BB 1, BB2, and BB3 is to supply register full or register eznpty
status inforznation for use by the shift control flip-flops.
For exaznple, if BB
1
is set, a buffer register Dl-full status is coupled to the SGl2 circuitry to
indicate that a character is in Dl and a transfer to D2 can be initiated.
Before
a transfer can occur, however, a buffer register D2-not full satus znust be
indicated by BB2.
The transfer frozn D2 to D3 is handled in znuch the sazne
znanner.
4-68
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