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A.
(NC=NO CONNECTION)
DiDS 68 576
DIDS-402-2AM13
B.
B
OR
A
NC
C
H
H
L
L
H
H
H
L
H
L
L
H
D.
~
~
c.
Figure 4-77.
Inverter {Driver Function, Logic Diagram. and Truth Table
4-31. 4
Edge-Triggered Flip-Flop
The sym.bol shown in Figure 4-78 represents an edge-triggered flip-flop.
When a high is applied to D, it is shifted to the Q output on. the positive transition
of the clock.
The flip-flop m.ay be jam.m.ed set or reset by applying a low input
pulse to the Pre set and Clear inputs re spectively.
4.31. 5
J
-K Master-Slave Flip-Flop
The sym.bols shown in figure 4-79 repre sent two variations of the
J-K
m.aster-slave flip-flops.
Part A illustrates a 7472N type logic elem.ent.
Input
AND-gates are used to AND the input signals for both the set and reset inputs.
However, since this flip-flop is a T2L elem.ent, a11 input connections need not be
connected in order to perform. the AND-function.
For exam.ple, if three pins
have external circuit connections, then a11 three inputs m.ust be high to satisfy
the input.
If, however, only two pins are connected externally,· then only these
two inputs m.ust be high to satisfy the input.
Part B i11ustrates 7473N type logic elem.ent.
In this elem.ent, satisfying
either the
J
or K input will set or reset the flip-flop.
Both circuits use the m.aster slave principle.
On the positive transition of
the clock, the rn.aster portion store s the input information and on the negative
·.transition of the clock the inform.ation appears at the slave outputs.
Unclocked
signals can be used on the jam. pin inputs; these signals override the norm.al
clocked inputs.
A
low input to preset (7472N only) sets Q to a logical
I
while a
low input to clear sets
Q
to a logical O.
The truth table (C) shown in figure
4-
79 shows the logical truth output of
each flip-flop when the given conditions are m.et.
In the case of the 7472N flip-
flop, a J input of
1
assum.es that all the three J inputs are satisfied, and a
K
input
of
1
assum.es that all three
K
inputs are satisfied.
4-168
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