Phase Counter, Logic Diagram; Minor Vertical Sweep And Phase Counter, Timing Diagram - Raytheon DIDS-400 Series Technical Manual

DIDS-402-2AMI3
counter and is therefore defined as the 'last' phase time. Once the phase and bit
counters are synchronized, the four phase outputs divide each bit into quarters
in a sequential order of 03, 04, 01, and 02 (figure 4-55). Since 02 defines the
last phase time of each bit, 03 pulses are employed to accomplish operations at
the beginning of a bit time and while the 02 pulses accomplish all operations
required at the end of the same bit time. Each of the pulse counter outputs is
active (high or low) for 0.203 !-Ls.
PHASE
COUNTER (.,.4)
12 9
A26 A26
MASTER CLOCK
13 8
.--..
A31
12
-----
I
A31
j j
-'"
I
A31
8
¢I
A21
. I!.
DIOS 68-652
-
Figure 4-54. Phase Counter, Logic Diagram
MASTER CLOCK
A26.12
A26.13
A26.9
. A26.B
A31. 12 - PHASE 3
A31.6 - PHASE 4
A31.B -PHASE I
A21.B - PHASE 2
'---_~r-
~
______
~n~
____
~nL
~
____
~f1~_~
___
~r1L..
____ __
u
U
...... t-t-.
203 IJS
A lB. 11 - PHASE 2 ;...... _ _ _ _
~nL..
____
....I1"'l-
OIDS 68-653
---..J
ONE BIT TIME
~
Figure 4-55. Minor Vertical Sweep and Phase
Counter, Timing Diagram
4-138