Buffer Register Di. Logic Diagram - Raytheon DIDS-400 Series Technical Manual

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DECODE
STX F,i1='oADDR F/F
...-_ _ _ _ ---, HI
~PARITY
CORRECT
PB
'ENTER HEADER
JAM PARITY
ERROR
DATA TO BUFFER
REGISTER 02
SET ADDRESS F/F
L--_ _ _ _ _ _ _ _ _ _ _ _
~~SET
STX F/F
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . . PERFORM LINE FEED
FUNCTION
...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. RESET STX AND ADDR
F/F'S (POLLII\!G)
8
INITIALIZE TRANSMIT
(POLLING'
DIDS 68-531 ERASE ETX
Figure 4-32. Buffer Register DI, Logic Diagram
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