Circuit Description; Description Of Section Contents - Raytheon DIDS-400 Series Technical Manual

DIDS-402-2AM13
SECTION III
CIRCUIT DESCRIPTION
4-21 DESCRIPTION OF SECTION CONTENTS
This section contains detailed circuit explanations of all digital and analog
boards contained in the Display Terminal. Wherever possible, information is
presented in sequential order taking care not to introduce subjects which have not
been previously discussed. In instances where information contained in later
explanations is required to understand the immediate text, the necessary infor-
mation is fully referenced by paragraph and/or figure number.
Logic elements used in the Display Terminal are contained in T2L integrated
circuits. It is a characteristic of these circuits that an open input is always high
Thus, if an AND-gate has three inputs and only two of those inputs are connected
to external sources, a true logic level at these two inputs will satisfy the gate.
In the circuit explanations, logic elements are referenced by location and
output pin number. Thus, A19.6 is located in the 19th integrated-circuit position
on board A12 and the output pin of the element is pin 6. To physically locate these
elements, refer to the parts layout drawings contained in Chapter 7.
4-22 COMMUNICATIONS CONTROL BOARD All
The purpose of the communications control board is to control the transfer
of digital information between the display terminal internal memllry and the CPU.
Circuits contained on this board work separately or in conjunction with one
another to perform the following major functions:
a. Transmit and Receive Enable - These circuits enable the Display
Terminal to enter either the transmit or the receive mode. Mode
selection is determined by interpreting locally issued or CPU
originated directives or controls. .
b. Parity Check and Generation - These circuits check the bit configura-
tion of each character transferred between the CPU and the Display
Terminal for the proper parity.
c. Buffer Registers and Decodes - These circuits provide a buffer
between the high- speed internal logic and the relatively slow- speed
transfer of data to and from the Display Terminal. Decodes con-
nected to the buffer registers enable the interpretation of various
digital control codes. The decoded outputs are used to initiate and
terminate data transfer and to accomplish edit or cursor control
functions.
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