Polling - Raytheon DIDS-400 Series Technical Manual

DIDS-402 -2AM13
4-22.2.2 Polling
In the polling conversational mode, the Display Terminal enters the
receive mode when characters STX and DA are received sequentially. As
stated in Section I, the address code, in addition to selecting the proper Display
Terminal, also contains a polling directive in the MSB position. If the MSB of
the address character is a 10 1 , the Display Terminal enters the receive mode to
prepare to write the incoming mes sage onto the CRT screen.
Conversely, if the
MSB of the address character is a Ill, the Display Terminal enters the transmit
mode since a polling read directive is indicated.
In the polling mode, one of three operational sequences is initiated depending
upon the addre s s character. The se sequence s are de scribed in the following text
by assuming the conditions listed below:
a. An incorrect address is received
b. A polling write directive is received
c. A polling read directive is received
For each of the following descriptions, it is assumed that an STX character
has been received. The reception of STX resulted in setting the STX flip-flop
(A79.l2) and resetting the ADDR flip-flop (A79. 9).
When an incorrect address is received following an STX character,
NAND-gate A82. 6 is not enabled. The high placed at the second input to NAND-
gate A71..3 is coupled through NOR-gate A80. 11 to enable NAND-gate A80. 8.
The output of A80. 8 is, in turn, inverted by NOR-gates A71.
11
and A71. 8 to
reset the ADDR and STX flip-flops, respectively. This returns the receive enable
circuit to its quiescent state (i. e., STXFjF and ADDRF/F).
When the correct address is decoded and a 10 1 is present in the MSB position,
the ADDR flip-flop is set by a high present at A 71. 6. Since a '0 I is present in the
MSB position, NAND-gate A 70.6 is inhibited from re setting the STX flip-flop.
When both the STX and APDR flip-flops are set, NAND-gate A 78.6 is enabled
to produce an RE output. This output continues to be present until an ETX
character is decoded in buffer register D3. The operation of the receive enable
circuit following a polling write directive is identical to the enquiry,.re sponse
mode, except for the necessity of inhibiting NAND-gate A70.6.
When the correct addre ss is decoded and a III is pre sent in the MSB
position, a polling read directive is indicated. As stated previously, the Display
Terminal responds to a read directive by entering the transmit mode. The 111
in the MSB of the address character enables the second input to NAND-gate A 70.6.
Thus, when the next phase A clock pulse is received, the ADDR flip-flop is set
and the STX flip-flop is reset. This produces an ADDR • STX condition to enable
AND-gate A81. 6 of the transmit enable circuitry (see figure 4-24).
4-65