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DIDS-402 -2AM13
code, NAND-gate All. 11 is enabled to produce the START XMIT pulse.
This
This initiates transmission beginning at the cursor position (first character of the
line) and terminating at the ETX position (up to 80 characters later on the same
line).
The function complete flip-flop then sequentially resets the one-step flip-
flop and the advance line flip-flop to return the circuit to its quiescent state.
4-22. 1. 3. 3 Enquiry Option
The enquiry (ENQ) option permits the CPU to initiate transmission from a
Display Terminal by simulating the manual depre ssion of the XMIT key.
In
either the enquiry-response or polling conversational modes, the CPU can insert
the ENQ control code into a message directed to a particular Display Terminal.
When ENQ is decoded in buffer register D3, a pulse which sets the ENQ flip-flop
(enquiry-re sponse) or simulate s the depression of XMIT (polling) is generated.
In either instance, transmission is initiated only after an ETX code is decoded
in the character e-ntry register (ETXSR).
If an ETX code has not been inserted
into memory, then transmission cannot occur.
Thus, ENQ is limited by the
same factors that govern local transmission (i. e., depressing XMIT or decoding
ENQ before an ETX code has been inserted into memory has no effect on the
transmit enable circuits).
The ENQ code is normally preceded in received messages by a cursor
reposition code.
This code moves the cursor to the position on the screen where
the CPU desires tp begin transmission.
If there is an ETX in memory, trans-
mission starts at the cursor position and ends at the position on the screen where
the ETX code was inserted by the operator (see figure 4-24).
In the polling conversational mode, the ENQ option is accomplished by
connecting a wire between terminals PG and PH.
When the ENQ code is received
and decoded in buffer register D3, NAND-gate A24.8 produces a low output.
This
low is connected to the set input of cross-connected flip-flop A64.l2.
As shown
in figure 4-24, decoding ENQ in D3 (ENQD3) has the same effect as depressing
the XMIT key.
The set output of A64. 12 forces A 72.6 low which, in turn, sets
flip-flop A 73.6 to enable one input of NAND-gate A64.8.
The circuit then rests
in this state until an ETX code is detected in buffer register Dl to indicate the
last character of the CPU message.
When ETX is received, a phase A pulse is gated through NAND-gate A63. 8
to disable the receive (R) steering logic and produce an Initialize Transmit pulse.
Also, when A 70.3 is set, inverter driver A 77.8 generates an Enter
HeaCl~r
pulse
to jam STX, DA and ETX into buffer registers D3, D2, and Dl, respectively.
Enter Header also sets flip-flop A 78. 11, which enables the second input to
NAND-gate A64. 8.
When ETX is found, the low output at A64. 8 clears BBI
and transmission is initiated.
If ETX is not detected in the memory loop, NAND-gate A64. 8 is not
enabled and transmission does not occur.
On
the next
F(~)
(frame pulse), a
complete scan of memory has been accomplished without finding an ETX code.
If an EOT or FF cursor reposition is not in effect, a CFR pulse is developed on
the display logic board and flip-flop A72.
6
is reset to disable the operation.
4-62
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