Parity Check And Generation; Receive - Raytheon DIDS-400 Series Technical Manual

DIDS-402-2AM13
4-22.3 Parity Check and Generation
The purpose of the parity check and generation circuitry is two-fold. In
the receive mode, the bit configuration of each received character is checked for
an even number of 11 S. If an erroneous character is received, the parity error
lamp is illuminated and a parity error SUB code (0011010) is inserted into
memory in place of the erroneous character. In the transmit mode, each trans-
mitted character is shifted through the parity check flip-flop and the number of
lIs is essentially counted.
If after one character time an odd number of lIs has
been counted, a parity bit of 1 is generated. Conversely, if an even number of lIs
is counted, a parity bit of 10 1 is generated to maintain even parity (see figure 4-27).
In either the transmit or the receive mode, the parity check flip-flop is
jammed reset by the decimal counter STT output. This output corresponds to
the first bit (b O ) of the 10-bit asynchronous characters used to convey information
between the Display Terminal and the CPU.
4-22.3. 1 Receive
In the receive mode, serial data is coupled directly from the interface
circuits and applied to one input of NAND-gate A48. 6. When the decimal
counter steps to the count following STT, the remaining input is satisfied and data
is permitted to pass through the gate to the J and K inputs of the parity check
flip-flop. The gate remains enabled until the decimal counter reache s the count
corresponding to the parity bit (PAR). In essence, this allows all seven data bits
to be Icounted
l
by the parity check circuitry to determine whether an even number
of lIs exists. After seven bit times, the parity check flip-flop may either be set
or reset, depending upon the number of lIs in the character.
If an odd number of
11 s is received, the flip-flop is set; if an even number of lIS is received, the
flip-flop is reset. The next bit of the character is then examined to determine
whether the received character had the correct number of ones.
The set and reset outputs of the parity check flip-flop are connected to
NAND-gates A45. 3 and A45. 8, respectively. The second input to NAND-gate
A45.3 is the inverse of data (DATA), and if the parity bit is a one, a zero is
pre sent at this point, while the input to NAND- gate A45. 8 is Itrue I data.
If an odd number of 11 s (one, three, five or seven) is
counted~
then to
achieve parity, the parity bit must also be alII. As'Surning that it is, NAND-gate
A45.3 is not enabled since DATA will be a 10 1 .
Since the received character had
the correct parity, no further circuit action is necessary. On the other hand,
consider what occurs when an odd number of ones are counted and the parity bit
is a 10 1 •
DATA will be a III and NAND-gate A48.6 is enabled during the next
phase A pulse. The low output jams a parity SUB code into buffer register Dl
Ion top ofl the erroneous character. Simultaneously, parity error flip-flop
A39.11 is set and the keyboard parity error indicator is illuminated. The
indicator remains illuminated until a master reset or Initialize Transmit pulse
resets the parity error flip-flop.
When an even nuznber of lIs is counted, the parity bit znust be a 10 1 to pro-
vide the correct parity. If it is not a 10', the reset output of the parity error
flip-flop and the parity error circuitry is enabled and the previously described
circuit action occurs.
4-66