Buffer Register D3, Logic Diagram - Raytheon DIDS-400 Series Technical Manual

LO~ENTERHEADER ~------------------------------------------------~~======~
________________
~
DATA FROM ... -------l
BUFFER REGISTER
02
LO
~INITIALIZE
TRANSMIT
DIDS 68-533
I!A
T
SG23
3 (CTS+I)
SOL
RE
ETXD3
SG23
4(CTS+I)
T
6
T
D3 GATE
12
DIDS-402 -2AM13
T
BA (TO TRANS-
MITTED DATA
A37
)------~
INTERFACE
8
CIRCUITS)
STP
6
~--------------------~DATA(RE)
(TO OUTPUT DISPLAY LOGIC)
Figure 4-34. Buffer Register D3,
Logic Diagram
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