Buffer Registers And Interface - Raytheon DIDS-400 Series Technical Manual

RECEIVED
DATA
LINE
.--
DI!:LAY LINE
DATA
OUT
PARITY CHECK
AND
GENERATION
RECEIVER
P/OAIA
AS6.5
I
JAM PARITY ERROR
DATA
MEMORY
DATA
I
BUFFER
REGISTER
~
01
P/O AI2
I
DECODES
::iTX
I
ADDR
lETX
BUFFER
P/O CHARACTER
1----...-1
ENTRY' REGISTER
NOTE: HEAVY LINE DENOTES DATA FLOW
DIDS 68-515
BUFFER
REGISTER
02 P/OAI2
JAM DA
BUFFER
REGISTER
02 P/O AI2
BUFFER
f---.
REGISTER
03 P/O AI2
I
DECODES
BEL BS
CR HT
NUL
CAN
LF FF
DC3 ESC VT DCI
ETX
JAM STX
BUFFER
REGISTER
03 P/O AI2
PARITY CHECK
AND
GENERATION
II>-BIT
CHARACTER
FORMING P/O AI4
DELAY LINE
i5'ATA
(RE)
CHARACTER
DATA IN
ENTRY
I
REGISTER P/O AI3
REFRESH MEMORY LOOP
TRANSMITTER
P/OAI4
START AND PARITY
BITS
STOP BIT
Figure 4-16. Buffer Registers and Interface
DELAY LINE
ELECTRONICS
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SEND
DATA
LINE
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