Buffer Registers - Raytheon DIDS-400 Series Technical Manual

DIDS-402 -2AM13
4-22.4.3 Buffer Registers
The Communications Control Board contains three 7-bit registers desig-
nated as buffer registers Dl. D2, and D3. The purpose of these registers is to
provide a buffer to compensate for the different rates used internally and
externally for transferring data.
Digital information is transferred between the Display Terminal and the
CPU at a rate of 1200 baud (120 10-bit characters per second). This transfer
rate corre sponds to a character time of 8.33 ms; thus, it takes 8.33 ms to either
transmit or receive one complete 10-bit character. This transfer rate is con-
trolled by an internal 1200-baud counter which develops 10 separate phase A
clock pulses for each character transferred between the devices (see paragraph
4 -24.9).
Internally" data is shifted through the buffer registers at a rate of 76.8 kHz,
or exactly 64 times faster than a character can be transmitted to or received
from the CPU. This transfer rate corresponds to 13 \JoS per character.
Figure 4-31 is a block 'diagram of the ,buffer registers. In the receive
mode, the buffer registers generally operate in the, following manner after the
receive enable circuitry is enabled. Data is coupled through the received data
interface circuits and applied to the input of Dl. The phase A clock, which starts
counting as soon as the character start bit is detected on the received data line,
produces seven clock. pulses to shift the incoming data into Dl. After 8.33 ms,
the first complete character is held in Dl, available for transfer to D2.
The transfer from Dl to D2 is enabled when SG12 permits applying seven
high-speed pulses to both registers simultaneously. This transfer takes approxi-
mately 13 \Jos. The transfer from D2 to D3 is handled in the same manner by
SG23 and after a minimum of 8.356 ms (8.33 ms
+
26 f.Ls), the character is con-
tained in D3. Simultaneously. another character may be entering Dl from the
received data line.
The character held in D3 remains there until the cursor is located in
memory. This can take from 0 to 16 ms, depending upon what point in time the
character was shifted into D3. For example, the cursor may have been shifted
through the character entry register just before the received character was
shifted into D3. If this is the case, 16 ms later the cursor reappears and the
character in D3 is inserted into memory via the character entry register.
From the character entry register. the character code is applied to the character
readout register and held for one character time. This results in displaying
the character associated with the code. The character code is simultaneously
serially shifted into memory where it refreshes the display presentation.
Since it takes 8.33 ms to receive one character, the three buffer registers
do not completely fill until 24.99 ms have elapsed. However, since the cursor is
located in a maximum of 16 ms. the buffer registers do not normally fill during
receive. An exception to this rule is when certain control codes which require
both locating the cursor (0 to 16 ms) and performing a time consuming edit or
cursor control operation (up to 16 ms) are received.
If this is the case, NULL
4-80