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DIDS-402-2AMI3
4-22.4.2.3 Shift (to/from) Delay Line (SDL)
The SDL circuitry is shown in figure 4-29.
The purpose of the SDL flip-flop
is to control the flow of data between the buffer registers and the delay line.
In the transmit mode, SDL is employed to enable clock pulses to Dl and
thereby shift data into the register from the delay line.
During this process, a
cursor right request (CRQ) pulse is developed to automatically step the cursor
one position to the right.
This permits the sequential extraction of one or more
characters each time the memory is accessed (provided, of course, that there
is room for the second character in the buffer registers).
In the receive mode, SDL is employed to enable clock pulses to D3.
Once
SDL is enabled, D3 GATE permits data from D3 to enter the memory via the
character entry register.
A CRQ pulse is also developed in the receive mode
sequence.
This pulse enables the entry of the next message character if a char-
acter is in D3 and available for transfer.
In addition to enabling data transfers to and from the delay line, SDL is
also employed to inhibit transfers under special conditions.
When control codes
are received as part of a message, SDL determines whether or not the control
code is entered into the delay line.
Because of the many different operating modes of SDL, the following text
contains separate descriptions of each mode.
These modes are categorized
and described as follows:
a.
Receive Mode
(1)
Text characters (such as letters, numerals ana. symbols)
(2)
Control characters when preceded by ESC
(3)
Control characters not preceded by ESC
(4)
Control characters DEL, ENQ, and NULL
b.
Transmit Mode
(I)
Text characters
In the SDL circuit quiescent state, a high is present at points A, B, C,
D, and E.
The circuit remains in this state until either RE or T goes high to
signify the beginning of a receive or transmit sequence.
4-22.4.2.3. I Receive Mode.;. Text Characters.
When the STX and DA
message header characters are received from the CPU, RE goes high to indi-
cate the presence of an incoming message.
This enables AND-gate A19. 8 and
places a high at one input of gates A23. 8 and A49.11.
A19.8 remains enabled
until RE is disabled or the CCC flip-flop is set by the reception of a control
code (see paragraph 4-22.4.4).
The circuit idles in this state until the charac-
ter following DA is shifted into buffer register D3 and BB3 is set.
The cursor,
which is constantly circulating through the character entry register, is located
4-75
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