Cursor Video, Logic Diagram - Raytheon DIDS-400 Series Technical Manual

DIDS-402-2AMI3
The 10-bit decimal counter is held reset by the 0A GATE level. This level
is present whenever the Display Terminal is neither transmitting nor receiving
data. The reset'condition is decoded by NAND-gate A38.12 which produces an
STP output. This level is used to hold the transmitted data line in a marking
condition.
When '/JA gate goes high as a result of the conditions previously described,
the counter is released. The first '/JA pulse clocks the counter to its first state
and NAND-gate A38. 8.is enabled to produce an STT output. This pulse resets
the parity-check flip-flop in preparation for checking
th~coming
(or outgoing)
character parity. When the counter steps from STP to STT, the transmitted
data line goes low to form the START bit.
During the next seven states of the counter, all three decodes are inhibited.
This enables the seven data bits of the character to be transmitted (or received).
During the following state, NAND-gate A38. 6 is enabled to produce the PAR
output. This output is in coincidence with the parity bit and is used to produce
the character parity bit (transmit) or to jam a parity error character into buffer
re gister DI (receive).
During the next state of the counter, an STP output is again produced to
place a stop bit .on the transmitted data line (transmit) and to re set the '/JA gate
circuitry (receive).
4-24. 10 Miscellaneous Circuits
4-24. 10. 1 Cursor Video
The backward L
(J )
cursor symbol is formed by the tirniitg miscellaneous
circuit shown in figure 4-68. The cursor symbol is composed of two separate
parts: a short line on the horizontal plane (-) and a longer line on a vertical
plane
(I ).,
When these two video outputs are combined, a,backward
L
(J )
cursor
symbol is produced. This symbol'is produc'ed in the following manner.
UNBLANKING
CURSOR
(HI DURING
3 CTS)
..... - - - - - 4 0
3 (CTS
+
I) ' - - - I C
012 MEM CLOCK
(HI
=>
01 OR 02)
A B
STEP UP .....--0
0 - - - '
r
C
Figure 4-68. Cursor Video,
Logic Diagram
6
} - - . , . CURSOR VIDEO
CURSOR-I
DIDS 68-567
When the cursor bit is detected in the CE register, the cursor input to
A34.5 goes high during 3CTS and remains high until 4(CTS+l) resets the cursor
located flip-flop. During 3(CTS+1), A34.5 goes high to enable one input to
NAND-gates A28. 3 and A22. 8. .
4-151