Buffer Register Dl - Raytheon DIDS-400 Series Technical Manual

DIDS-402 -2AM13
characters are used to provide time-fill between the control code and the next
information character of the message. This, in turn, prevents losing valid
information when the registers fill to capacity and then overfill due to the
continuous transfer of data into Dl.
In the transmit mode, the buffer registers provide a smooth release of
data from the delay line to the CPU even though the memory is accessible only
once every 16 ms. Each time the cursor appears in the character entry register,
one and usually two characters can be extracted from the memory and shifted
into the buffer registers. The transfer from memory, as well as the subsequent
transfers from Dl to D2 and D2 to D3, occurs at the high-speed rate of 13
~s/
character. Because of the much slower transmission rate, the characters stack
up and the read from the delay line must be terminated by releasing the cursor.
In the 16 ms it takes for the cursor to once again appear in the character entry
register, nearly two characters (16.66 ms) can be shifted out of D3 to the CPU.
Since there are three buffer registers, however, a third character is always
available for transfer to D3 even though 16 ms have elapsed since the last
time the memory was acce s sed. This feature provide s a steady stream of
serial data from D3 to the CPU.
4-22.4.3. 1 Buffer Register Dl. Buffer register Dl and the Dl decode s are
shown in figure 4-32. The register consists of seven D-type flip-flops which
share the common clock inputs from inverter-driver A14. 6. The operation of
Dl in first the receive and then the transmit modes of operation are briefly
outlined below.
In the receive mode, each time a start bit is detected on the received data
line, the 1200-baud counter begins counting up to 10 (see paragraph 4-24.9).
As soon as the decimal counter reaches a count corresponding to the first data
bit (i. e., STT and STP and PAR, NAND-gate A47. 8 is enabled and seven phase A
pulse s are applied through A14. 6 to the clock input of each register flip-flop.
These seven pulses shift the incoming character into Dl through A61. 3 regardless
of the bit configuration of the character. (R is always high unless the Display
Terminal is transmitting data. )
If a valid mes sage is being received, the fir st character shifted into Dl
should be STX.
If this is the case, during the STX character parity count,
STX decode A 75.8 is enabled to set the STX flip-flop. The STX character is
held in Dl until the decimal counter cycles through the counts STP (of STX) and
STT (of ADDR). Again, seven phase A pulses are applied through A14. 6 to
shift the next character into Dl. The Display Terminal interprets this code
to determine whether it corresponds to a previously hard-wired address code.
If the character received is the proper DA, ADDR decode A83. 8 is enabled to
set the ADDR flip-flop during the parity count. This, in turn, develops an RE
level which permits all successive characters to enter buffer register D2. The
next character of the message is shifted into Dl in a similar manner, except
that this time the phase A pulse occurring during PAR is used to set BBl during
l(CTS+1). BBl, in turn, enables SGl2 during 4CTS, and seven fast-clock pulses
[beginning with 3(CTS+2)] are applied to Dl through NAND-gate A49. 8. These
pulse s serially shift the character out of Dl and into D2. While this is occurring
(it takes 13
~s),
the decimal counter is cycling through- STP and STT (830
~s).
Thus, by the time the condition STP, STT, and PAR is once again true, DI is
empty and prepared to accept the next character of the message.
4-83