Polling - Raytheon DIDS-400 Series Technical Manual

DIDS-402-2AM13
While data is being entered or extracted from memory, a special flip-flop
in the steering logic, shift delay line (SDL), is enabled. Thus during the transmit
mode, all three inputs to AND-gate A57. 12 are satisfied during 3(CTS+l) each
time SDL is enabled. The output of this gate (which consists of a pulse in coin-
cidence with each extracted character) is applied to one input of NAND-gate A59. 8.
When the last character of the message (ETX) is shifted into buffer register Dl,
A59.8 is enabled to set flip-flop AlO. 8. The flip-flop, once set, enables one of
the inputs to NAND-gate A26.6. When the ETX code detected in Dl is finally
shifted out of the last buffer register, all three registers are empty. This
empty condition is sensed by 'busy-bit' flip-flops BB 1, BB2, and BB3 on the
Communications Control Board and the 'not full' levels enable AND-gate A8l. 12.
Since T is still high, the next phase 3 timing pulse is gated through NAND-gate
A26.6 to set flip-flop A39. 8. On the next
F~
04 pulse, the transmit time-out
flip-flop is set and, simultaneously, A39.6 is reset to remove the input. On the
rising edge of the next
F'~04
pulse (16 ms later), NAND-gate A55. 11 is enabled
and a transmit time-out pulse is generated. This pulse is used to reset flip-flops
A62.8, A62.l2, and A50. 12, and thus disable the T steering logic and the request-
to-send line. Simultaneously, since the output at A62. 12 is high, the R steering
logic is now enabled.
On the trailing edge of the F..1.04 pulse that enabled NAND-gate A55. 11, the
transmit time-out flip-flop is reset and the transmit-receive enable circuitry
returns to its quiescent state.
4-22. 1. 2 Polling
In the polling conversational mode, both sections of the transmit and
receive enable circuitry work closely in conjunction, since the Display Terminal
must receive a polling read directive before it can transmit the message contained
in the delay line.
The operator types in the message in the usual fashion and then sequentially
depresses the END and XMIT keys. As stated previously, depressing the END
key places an ETX character code into mem.ory where it is constantly circulated
(see figure 4-24).
When the operator depresses the XMIT key. the resulting keyboard output
level is combined with a sample strobe (XMIT PLSE) to enable NAND-gate All. 11.
The output of A21.11 sets flip-flop A64.l2 which, in turn, sets flip-flop A73.6.
This enables one input to NAND-gate A64.8, and the transmit enable circuitry
idle s until a polling command is received from the CPU.
The Display Terminal rests in the receive state (R=high) to allow receipt
of the polling message. Note that either a read or a write directive can be
issued by the CPU. !fa read directive is issued, the Display Term.inal enters
the transmit mode and transfers the message stored in the delay line to the CPU.
On the other hand, the CPU may issue a write directive, since it has no way of
knowing that the operator has a message available for transfer.
If this occurs,
the Display Terminal enters the receive mode and the stored me ssage is
partially or completely de stroyed, depending upon the length of the received
m.essage.
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