Mch Power Delivery Guidelines; Ddr_Vtt (1.25 V) Decoupling; Cpu_Vcc (1.05 V Power Plane); Intel ® Pentium ® M Processor Gtlref0 Voltage Divider Network - Intel Pentium M Processor Design Manual

HDVREF[3:0], HAVREF[1:0], HCCVREF pins. The GTLREF voltage divider for both the Intel
®
Pentium
their own locally generated GTLREF networks.
generating GTLREF for the Intel Pentium M processor using a R1 = 1 k ± 1% and R2 = 2 k ± 1%
resistive divider.
Since the input buffer trip point is set by the 2/3* V
voltage fluctuations, no decoupling should be placed on the GTLREF pin. The node between R1
and R2 (GTLREF) should be connected to the GTLREF pin of the Intel Pentium M processor with
a Zo = 50 trace shorter than 0.5 inches. Space any other switching signals away from GTLREF with
a minimum separation of 25 mils. Do not allow signal lines to use the GTLREF routing as part of
their return path (i.e., do not allow the GTLREF routing to create splits or discontinuities in the
reference planes of the Intel Pentium M processor system bus signals).
®
Figure 136. Intel Pentium
1K Ω
2K Ω
11.4

MCH Power Delivery Guidelines

The following guidelines are recommended for an optimal MCH power delivery. The main focus
of these guidelines is to minimize chipset power noise and signal integrity problems. The
guidelines are not intended to replace thorough system validation of products.
11.4.1

DDR_VTT (1.25 V) Decoupling

To reduce noise on the DDR termination voltage (1.25 V) around the MCH, four 0.1 µF capacitors
per-channel are recommended. Evenly distribute placement of decoupling capacitors along the
VTT plane around the MCH within one inch of the outer row of balls. Ceramic 0603 body type
capacitors are recommended.
11.4.2

CPU_VCC (1.05 V Power Plane)

®
The Intel
1.05 V power plane. This voltage powers the GTL Processor System Bus.
•
Five, 0.1 µF capacitors are recommended (with 900 pH to 1.1 nH inductance) to be placed
under the MCH for System Bus 1.05 V power plane decoupling.
Design Guide
®
Intel Pentium
M processor and MCH cannot be shared. Thus, both the processor and MCH must have
®
M Processor GTLREF0 Voltage Divider Network
+ VCCP
R1
1%
GTLREF
R2
1%
E7501 chipset's CPU_VCC pins and the Processor's V
®
M Processor and Intel
Platform Power Delivery Guidelines
Figure 136 shows the recommended topology for
on GTLREF and to allow tracking of V
CCP
<0.5"
Ω
Zo = 50 trace
GTLREF0
(pin AD26)
®
Pentium
RSVD
N/C
(pin E26)
®
E7501 Chipset Platform
RSVD
(pin AC1)
®
Intel
M Processor
RSVD
(pin G1)
pins are connected to the
CCP
®
CCP
N/C
N/C
203