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®
®
Intel
Pentium
M Processor and Intel
Debug Port and Logic Analyzer Interface
10.2.1.4
RESET# Routing Guidelines
As explained in
Figure 26
®
Intel
Pentium
length) and ITP700FLEX debug port. One branch from the fork connects to the Intel Pentium M
processor's RESET# pin and the second branch connects to a 54.9 Ω ± 1% termination pull-up
resistor to V
to continue the path to the ITP700FLEX RESET# pin with the RESETITP# net in
The length of the RESETITP# net (labeled as net L4) should be limited to be less than 0.5 inches.
To ensure correct operational timings, the length of the RESET# nets L3, L4, and L5 with respect
to the BPM[4:0]# net length L2 should adhere the following length matching requirement within
± 50 ps.
There is no need for pull-up termination on the Intel Pentium M processor side of the RESET# net
due to presence of AGTL+ on-die termination on the processor and the Intel E7501 MCH.
10.2.1.5
BCLK Routing Requirements
The ITP700FLEX debug port's BCLKp/BCLKn inputs are driven with a 100-MHz differential
clock from the CK-408 clock chip and require 33
two pairs of 100-MHz differential clocks to the Intel Pentium M processor's BCLK[1:0] and Intel
E7501 chipset's BCLK[1:0] input pins. Common clock signal timing requirements of the Intel
E7501 MCH and the Intel Pentium M processor requires matching of processor and MCH
BCLK[1:0] nets L6 and L7, respectively. To ensure correct operation of the ITP700FLEX, the
BCLKp/BCLKn net L8 should be tuned to be within ± 50 ps to the sum of length L6 of the
BCLK[1:0] lines and the additional length L2 of the BPM#[4:0] signals.
10.2.1.6
ITPFLEX Routing Requirement Summary
The timing requirements for the BPM[5:0]#, RESET#, and BCLKp/BCLKn signals of the
ITP700FLEX debug port requires careful attention to their routing. Standard high frequency bus
routing practices should be observed.
1. Keep a minimum of 2:1 spacing in between these signals and to other signals.
2. Reference these signals to ground planes and avoid routing across power plane splits.
3. The number of routing layer transitions should be minimized. When layout constraints require
a routing layer transition, any such transition should be accompanied with ground stitching
vias placed within 100 mils of the signal via with at least one ground via for every two signals
making a layer transition.
The ITP700FLEX VTT and VTAP pins should be shorted together and connected to the VCCP
(1.05 V) plane with a 0.1 µF decoupling capacitor placed within 0.1 inch of the VTT pins.
Table 85
connect to for proper operation for onboard ITP700FLEX debug port.
182
®
E7501 Chipset Platform
Section 5.1.4.2, "Processor RESET# Signal"
and
Figure
125) out from the Intel
®
M processor (because of this fork, the L5 segment is subtracted from the total
placed close to the ITP700FLEX debug port. A series 22.6 Ω ± 1% resistor is used
CCP
L3 + L4 – L5 = L2 (within ± 50 ps)
L6 + L2 = L8 (within ± 50 ps)
summarizes termination resistors values, placement, and voltages the ITP signals need to
the RESET# signal forks (see
®
E7501 MCH's CPURESET# pin and is routed to the
Ω
series resistors. The CK-408 also feeds another
Figure
125.
®
®
Design Guide
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