Asynchronous Signals; Topologies; Internal Layer Routing Guidelines - Intel Pentium M Processor Design Manual

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®
Table 22. Intel Pentium

Internal Layer Routing Guidelines

Signal Names
CPU
ADS#
BNR#
BPRI#
BR0#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
LOCK#
RS[2:0]#
TRDY#
RESET#
† For topologies where an ITP700FLEX debug port is implemented, see
RESET# Signal"
5.1.7

Asynchronous Signals

5.1.7.1

Topologies

The following sections describe the topologies and layout recommendations for the Asynchronous
Open Drain and CMOS signals (see
in the following sections below must be pulled-up to V
Drain signals are pulled-up to a voltage higher than V
the processor may be affected. Therefore, it is very important to follow the recommended
termination voltage for these signals.
5.1.7.1.1 Topology 1A: Open Drain (OD) Signals Driven by the Intel
IERR#
The Topology 1A OD signal IERR# should adhere to the following routing and layout
recommendations.
®
the Intel
micro-strip or strip-lines using 50 Ω ± 10% characteristic trace impedance. Series resistor R1 (see
Figure 27) is a dampening resistor for reducing overshoot/undershoot reflections on the
transmission line. The pull-up voltage for termination resistor R
dependencies on system design implementation, IERR# may be implemented in a number of ways
to meet design goals. IERR# may be routed as a test point or to any optional system receiver.
Design Guide
®
Intel Pentium
®
M Processor System Bus Common Clock Signal
Transmission Line
MCH
ADS#
BNR#
BPRI#
BREQ0#
DBSY#
DEFER#
DRDY# Strip-line
HIT#
HITM#
HLOCK#
RS[2:0]#
HTRDY#
†
CPURST#
for RESET# (CPURESET#) implementation details.
Table 23 lists the recommended routing requirements for the IERR# signal of
®
Pentium M processor. The routing guidelines allow the signal to be routed as either
®
M Processor and Intel
System Bus Routing Guidelines
Total Trace Length
Type
Min
(inches)
3.0
Table 14) found on the platform. All Open Drain signals listed
(1.05 V). When any of these Open
CCP
, the reliability and power consumption of
CCP
®
E7501 Chipset Platform
Normal
Impedance
Max
(Ω)
(inches)
7.5 50 ± 10%
Section 5.1.4.2, "Processor
® ®
Pentium M Processor –
is V (1.05 V). Due to the
tt CCP
Width and
spacing
(mils)
4 and 8
65