Intel Pentium M Processor Design Manual page 273

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Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 3 of 4)
Checklist Items
CKE_x
RCVEN_x#
DDRCOMP_x
DDRCVO_x
DDRVREF_x[3:0]
Decoupling
General
Guidelines
Design Guide
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Intel Pentium M Processor and Intel
Recommendations
• Route 40 Ω using a 7.5 mils wide trace.
• The CKE signal must be length matched
to the clock signal at each DIMM within
two inches.
• Place termination resistor within 800 mils
from last DIMM connector. When routing
creates stubs, keep the stub length less
than 300 mils.
Route 50 Ω using a 5-mil wide trace with
15-mil wide spacing. Use topology in
Table 38 or Table 48.
Route 15 mils wide trace with 20 mils wide
spacing. Place pull-up resistor within one inch
of the MCH.
Route 15 mils wide trace with 20 mils wide
spacing. Place resistive network within one
inch of the MCH.
Place a 0.1 µF capacitor next to each MCH
pin.
• Spread termination decoupling
capacitors evenly around the termination
plane.
• Spread 2.5 V decoupling capacitors
evenly around the DIMMs.
Hub Interface
• Hub interface data spacing of 5 /15 (1:3)
is maintained for data, and 5/35 (1:7) for
strobes.
• Space signals out as much as possible
on breakout from the BGA.
• Hub interface data group signals are
routed on the same layer, transitioning
together when a layer change is
required.
• Maximum length of 20 inches (stripline
routing).
• Length match Hub Interface 2.0 strobes
within one inch from data. Length match
according to Figure 75.
• Hub Interface 1.5: Length match data
± 100 mils and strobes ± 1mil.
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E7501 Chipset Platform
Layout Checklist
Comments
• For dual channel, refer to
Section 6.3.5.
• For single channel, refer to
Section 6.4.6.
• For dual channel, refer to
Section 6.3.6.1.
• For single channel, refer to
Section 6.4.7.1.
• For dual channel, refer to
Section 6.3.6.2.
• For single channel, refer to
Section 6.4.7.2.
• For dual channel, refer to
Section 6.3.6.4.
• For single channel, refer to
Section 6.4.7.4.
• For dual channel, refer to
Section 6.3.6.3.
• For single channel, refer to
Section 6.4.7.3.
• For dual channel, refer to
Section 6.3.7.
• For single channel, refer to
Section 6.4.8.
Refer to Section 7.2.1 and Section 7.3.1
of this document.
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