Single Channel Ddrvref And Odtcomp; Single Channel Ddrcomp Resistive Compensation - Intel Pentium M Processor Design Manual

Table 49. DDRCOMP Routing Guidelines
Topology
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH to Rtt
Termination Resistor (Rtt)
Termination Voltage
Figure 66.

Single Channel DDRCOMP Resistive Compensation

6.4.7.2.1 DDRCOMP Tuning
It may be necessary to tune the DDR memory bus for optimum signal integrity based on your
platform characteristics. If the signal quality of the memory bus needs to be tuned, then it is
recommended that the DDRCOMP_A resistor value be adjusted to achieve optimum signal quality.
The 24.9 Ω resistor is used as a starting point and may or may not need to be adjusted depending on
your board characteristics.
6.4.7.3

Single Channel DDRVREF and ODTCOMP

The DDR system memory reference voltage (VREF) is used by the DRAM devices and the MCH
to determine the logic level being driven on the data, command, and control signals. VREF of the
receiving device must track changes in VTERM to maximize DDR interface margin. However,
VTERM and VREF cannot be the same power plane due to the sensitivity of the DRAM VREF
buffers to the termination plane noise. When a voltage regulator is used, it must reference VTERM
(see Figure
source voltage between them (i.e., both VREF and V
Use equal value 1% resistors to derive DDR VREF (see
divider and DIMMs/MCH using one 0.1 µF capacitor per VREF pin.
Design Guide
®
Intel Pentium
Parameter
pull-down
15 mils
20 mils
< 1.0"
24.9 Ω ± 1%
Ground
M C H
D D R C O M P _ A
67). When a local resistor divider is used, VREF and VTERM must have a common
®
M Processor and Intel
Memory Interface Routing Guidelines
®
Intel E7501 MCH
< 1 "
2 4 .9 Ω ± 1 %
are derived from the same voltage plane).
TT
Figure 68). Decouple VREF locally at the
®
E7501 Chipset Platform
105