Voltage Regulator Topology - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
Platform Power Delivery Guidelines
These technology improvements by themselves are not sufficient to effectively remove the heat
generated during the high current demand and tighter voltage regulation required by today's
processors. There are several mechanisms for effectively removing heat from the package of these
integrated devices. Some of the most common methods are listed below.
•
Attaching a heat spreader or heat pipe to the package with a low thermal co-efficient bonding
material.
•
Adding and/or increasing the copper fill area attached to high current carrying leads.
•
Adding or redirecting air flow to flow across the device.
•
Utilize multiple devices in parallel, as allowed, to reduce package power dissipation.
•
Utilizing newer/enhanced technology and devices to lower heat generation but with equal or
better performance.
For the system designer, these options are not always available or economically feasible. The most
effective method of thermal spreading and heat removal, from these devices, is to generate airflow
across the package and add copper fill area to the current carrying leads of the package.
The processor power delivery topology may also be modified to improve the thermal spreading
characteristic of the circuit and dramatically reduce the power dissipation requirements of the
switching MOSFET and inductor. This topology referred to as multi-phase, provides an output
stage of the processor regulator consisting of several smaller buck inductor phases that are summed
together at the processor. Each phase may be designed to handle and source a much smaller
current. This may reduce the size, quantity, and rating of the components needed in the design. This
may also decrease the cost and PCB area needed for the total solution.
11.3.6

Voltage Regulator Topology

In a single-phase topology, the duty cycle of the Control (top) MOSFET is roughly the ratio of the
output voltage and the input voltage. Due to the small ratio between V
cycle of the Control MOSFET is very small. The main power loss in the Control MOSFET is
therefore due to the transition or switching loss as it switches on and off. To minimize the transition
loss in the Control MOSFET, its transition time must be minimized. This is usually accomplished
with the use of a small-size MOSFET. Or similarly, the duty cycle of the Synchronous MOSFET is
very large; hence, to minimize the DC loss of the Synchronous MOSFET, its R
small. This is usually accomplished with the use of a large-size MOSFET or several small-size
MOSFETs connected in parallel, but this solution usually leads to shoot-through current as it is
quite difficult to minimize the effect of the Gate-Glitch phenomenon in the Synchronous MOSFET
due to C
GD
multi-phase topology, the output load current is sourced from multiple sources or output stages.
The term multi-phase implies that the phases or stages are out of phase with respect to each other.
For example, in a dual-phase topology, the stages are exactly 180 ° output of phase.
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E7501 Chipset Platform
charge coupling effect. Therefore, it is necessary to go to multi-phase topology. In a
and V , the duty
CC_CORE DC
must be
DS-ON
Design Guide