Reference Schematic For Serial Mode; Intel ® P64H2 Pci Interface Pcixcap And M66En Pins; Pcixcap Pin Requirements - Intel Pentium M Processor Design Manual

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®
®
Intel
Pentium
M Processor and Intel
®
Intel
82870P2 (Intel P64H2)
8.2.9.8

Reference Schematic for Serial Mode

The schematic in
Note: This schematic has not been fully validated.
Figure 103.

Reference Schematic for Serial Mode

PxPCLKO [0:6]
7
PxPCLKO [1:3] to
clock bus logic for PCI
Feedback from
slots [1:3].
PxPCLK 6
PxPCLKI
PxAD[63:0]
64
PxC/BE[7:0]
PxPAR
PxPAR64
PxREQ64#
PxACK64#
PxFRAME#
PxIRDY#
PxTRDY#
PxSTOP#
PxDEVSEL#
PxPLOCK#
PxPERR#
PxSERR#
PxREQ[0:5]#
6
PxGNT[0:5]#
6
PxM66EN
6
PxM66EN must be be
routed to each PCI Slot
by means of a bus
3.3V
®
switch so that the Intel
828702P2 can drive this
signal when appropriate
PxPCIXCAP
8.2K
HPx_SIC
HPx_SIL#
HPx_SID
HPx_SOR#
HPx_SORR#
HPx_SOC
HPx_SOL
HPx_SOLR
HPx_SOD
HPx_SLOT2
HPx_SLOT1
HPx_SLOT0
8.2K
HPx_SLOT[2:0]
100b for 4 slots
serial
®
8.2.10
Intel
8.2.10.1

PCIXCAP Pin Requirements

During all modes of the Intel P64H2 Hot-Plug controller operation, the Intel P64H2 PCI/PCI-X
interface pin PxPCIXCAP is not used. This pin should be tied to VCC3_3 through an 8.2 kΩ
resistor to avoid having this line float.
The slot-specific HxPCIXCAP1 and HxPCIXCAP2 pins should be connected to their associated
slot. See
Section
PCI/PCI-X capability.
148
®
E7501 Chipset Platform
Figure 103
is based on definition and simulation of the Intel
33
Reset [2:4] to PCI
33
Slots [2:4]
97
Some signals are
bidirectional, others
Busen [2:4] to
are not. Pull-ups are
bus enable logic
not shown for PCI
for PCI slots [2:4]
Control Signals. Refer
to the PCI
specification for these
values.
3.3V
Clken [2:4] to bus
enable logic for
PCI slots [2:4]
5K
Pwren [2:4] to power
enable logic for PCI slots
[2:4]
Amber LED 1
Amber LED 4
HPx_SIC
HPx_SIL#
HPx_SID
HPx_SOR#
HPx_SORR#
HPx_SOC
HPx_SOL
One of These
HPx_SOLR
for Each Slot
HPx_SOD
SLOT 1 Fault#
SLOT 1 Switch
3.3V
SLOT 1 Present 1
SLOT 1 Present 2
SLOT 1 M66EN
8.2K
8.2K
SLOT 1 PCIXCAP 1
SLOT 1 PCIXCAP 2
Serial/Parallel Logic
P64H2 PCI Interface PCIXCAP and M66EN Pins
8.2.7,
Section
8.2.8, and
97
Reset [1:4] #
4
87
Busen [1:4]
4
Clken [1:4]
4
Pwren 1
Pwren [1:4]
4
GPOA [7:0]
Green LED 1
330
.
.
.
330
.
Green LED 4
Same as above
5K
3.3V
5K
3.3V
8.2K
3.3V
Comparator
8.2K
Comparator
Section 8.2.9
for more information on properly decoding
®
P64H2.
To PCI Slots 2-4
RST #
64
PxAD[63:0]
PxC/BE[7:0]
PxPAR
PxPAR64
PCI BUS SIGNALS
PxREQ64#
PCI BUS SIGNALS
PxACK64#
PxFRAME#
Slot 1 Bus
87
PxIRDY#
Busen#
Switch
PxTRDY#
PxSTOP#
PxDEVSEL#
PxPLOCK#
PxPCLKO 0
PxPERR#
PxSERR#
Slot 1 Clock
PxREQ0#
Switch
PxGNT0#
Clken#
PxPCLKO 0
CLK
Slot 1
--12V
--12V
Power Logic
+12V
+12V
Pwren 1
+5V
+5V
Fault#
+3V
+3V
Depending on the
3.3V
serialization/
deserialization
10K
logic used, the
switch may have
to be debounced.
SLOT 1 Present 1
SLOT 1 Present 2
3.3V
5K
Isolation
logic
3.3V
M66EN
10K
3.3V
3.3V
5.6K
10K
2.2K
PCIXCAP
10K
Design Guide

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