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Table 72.
Loop Clock Configuration Routing Length Parameters
Clock Speed / Configuration
66 MHz / With HP
100 MHz / No HP
100 MHz / With HP
133 MHz / No HP
133 MHz / With HP
† L
must be the same length (± 25 mils) as any device clock length on the same bus. If a device is down on
fbi
the motherboard, L
for L2 and
8.1.8
IDSEL Implementation
Designers should use a 100 Ω series coupling resistor on the IDSEL signal when implementing
PCI-X. Though the PCI-X Addendum PCI Local Bus Specification, Revision 1.0, calls for a 2 kΩ
resistor, the current specification, PCI-X Addendum to the PCI Local Bus Specification, Revision
1.0a, allows for other resistor values. See
coupling resistor. IDSEL mapping per Intel
Figure 93.
IDSEL Sample Implementation Circuit
8.1.9
SMBus Address
The SMBus interface does not have configuration registers. The SMBus address is set by the states
of pins PAGNT[5:4] and PBGNT[5:4] when PWROK is asserted as described in
®
the Intel
®
Intel
P64H2 strap latching.
Design Guide
®
Intel
Pentium
33 MHz / No HP
66 MHz / No HP
= L2. If a devices is on an expansion card, L
fbi
Figure 92
for L
.
fbi
®
Intel
P64H 2
IDS EL0
IDS EL1
IDS EL2
IDS EL3
82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) Datasheet for a more detailed description of
®
M Processor and Intel
L
(inches)
fbo
3.5 – 5.5
4.5 – 5.5
0.25 – 1.0
≤ 1.0
4.5 – 5.5
0.25 – 1.0
3.5 – 4.0
Figure 93
for an example of how to implement the
®
P64H2 pin is arbitrary. However, AD16 is reserved.
Ω
100
Ω
100
Ω
100
Ω
100
®
E7501 Chipset Platform
®
Intel
82870P2 (Intel P64H2)
L
(inches)
fbi
2.9 – 7.9
3.9 – 4.9
7.0 – 12.0
†
L2 + 2.5
3.9 – 4.9
†
L2 + 2.5
5.5 – 5.7
= L2 + 2.5 inches. Refer to
fbi
Table
73. Refer to
Figure 91
131
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