Juniper ACX2000 Hardware Manual page 37

Table 5: Protocols and Applications Supported by ACX Series Routers (continued)
Protocol or
Application
Synchronous Ethernet
Building-integrated
timing supply (BITS)
Clock synchronization
Redundant clock
(multiple 1588 masters)
Transparent clock
Grand Master Clock
OAM, Troubleshooting, Manageability, Lawful Intercept
A C X 1 0 0 0 A C X 1 1 0 0 A C X 2 0 0 0
12.2 12.2R2 12.2
12.2 12.2R2 12.2
12.2 12.2R2 12.2
– – –
– – –
– – –
A C X 2 1 0 0 A C X 2 2 0 0 A C X 4 0 0 0
12.2R2 12. 3 X54 12. 3 x51
–D15 -D10
12.2R2 12. 3 X54 12. 3 x51
–D15 -D10
12.2R2 12. 3 X54 12. 3 x51
–D15 -D10
– – –
– – –
– – –
A C X 5 0 4 8 A C X 5 0 9 6 A C X 5 0 0
– – 12. 3 X54
–D20
(Indoor)
12. 3 X54
–D25
( O utdoor)
– – 12. 3 X54
–D20
(Indoor)
12. 3 X54
–D25
( O utdoor)
– – 12. 3 X54
–D20
(Indoor)
12. 3 X54
–D25
( O utdoor)
– – –
15. 1 X54 15. 1 X54 –
–D20 –D20
– – 12. 3 X54
–D20
and
17.3R1
(Indoor)
12. 3 X54
–D25
( O utdoor)
37
A C X 5 4 4 8
18.2R1
-
-
-
18.2R1
-