Chapter 14: 10/100 Ethernet Physical Layer Interface; Ethernet Phy Connections - Xilinx Spartan-3A User Manual

Chapter 14: 10/100 Ethernet Physical Layer Interface

Ethernet PHY Connections

The FPGA connects to the LAN8700 Ethernet PHY using a standard Media Independent
Interface (MII), as shown in
signals, including the FPGA pin number, appears in
Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY
118
FPGA
See Table
(D8)
(B2)
(E11)
See Table
(H10)
(G10)
(C12)
(H12)
(G12)
(D10)
(E10)
(D15)
Figure 14-2: FPGA Connects to Ethernet PHY via MII
FPGA Pin
Signal Name
Number
E_TXD<4> B2
E_TXD<3> F7
E_TXD<2> E6
E_TXD<1> E7
E_TXD<0> F8
E_TX_EN D8
E_TX_CLK E11
E_RXD<4> G10
E_RXD<3> H9
E_RXD<2> G9
E_RXD<1> G8
E_RXD<0> G7
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Figure 14-2. A more detailed description of the interface
SMSC LAN8700
10/100 Ethernet PHY
E_TXD<3:0>
TXD[3:0]
E_TX_EN
TX_EN
E_TXD<4>
TXD4/TX_ER/nINIT
E_TX_CLK
TX_CLK
E_RXD<3:0>
RXD[3:0]
E_RX_DV
RX_DV
E_RXD<4>
RXD4/RX_ER
E_RX_CLK
RX_CLK
E_CRS
CRS/PHYAD4
E_COL
COL_MII_CRS-DV
E_MDC
MDC
E_MDIO
MDIO
E_NRST
nRST
Transmit Data to the PHY. E_TXD<4> is also the MII
Transmit Error.
Transmit Enable
Transmit Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in
10Base-T mode.
Receive Data from the PHY
Spartan-3A/3AN Starter Kit Board User Guide
Table 14-1.
Connector
(integrated
magnetics)
25.000 MHz
UG334_c14_02_052407
Function
UG334 (v1.0) May 28, 2007
R
RJ-45