Keyboard - Xilinx Spartan-3A User Manual

Chapter 8: PS/2 Mouse/Keyboard Port
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a
host device, the FPGA in this case. The PS/2 bus includes both clock and data. Both a
mouse and keyboard drive the bus with identical signal timings, and both use 11-bit words
that include a start, a stop, and an odd parity bit. However, the data packets are organized
differently for a mouse and keyboard. Both the keyboard and mouse interfaces allows
bidirectional data transfers. For example, the FPGA host design can illuminate the state
LEDs on the keyboard or change the communicate rate with the mouse.
The PS/2 bus timing appears in
only driven when data transfers occur; otherwise they are held in the idle state at a logic
High. The timing defines signal requirements for mouse-to-host communications and
bidirectional keyboard communications. As shown in
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
Table 8-2: PS/2 Bus Timing

Keyboard

The keyboard uses open-collector drivers so that either the device or the host can drive the
two-wire bus. If the host never sends data, then the host can use simple input pins.
A PS/2-style keyboard uses scan codes to communicate key-press data. Each key has a
single, unique scan code that is sent whenever the corresponding key is pressed. The scan
codes for most keys appear in
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends an "F0" key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed or
not. The host determines which character is intended.
Some keys, called extended keys, send an "E0" ahead of the scan code, and furthermore,
they might send more than one scan code. When an extended key is released, an "E0 F0"
key-up code is sent, followed by the scan code.
66
Symbol
T
Clock High or Low Time
CK
T
Data-to-clock Setup Time
SU
T Clock-to-data Hold Time
HLD
CLK (PS2C)
DATA (PS2D)
Figure 8-2: PS/2 Bus Timing Waveforms
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Table 8-2 and Figure
Parameter
T T
CK CK
Edge 0
T
HLD
T
SU
'0' start bit
Figure 8-3.
Spartan-3A/3AN Starter Kit Board User Guide
8-2. The clock and data signals are
Figure 8-2, the attached keyboard or
Min Max
30 μs 50 μs
5 μs 25 μs
5 μs 25 μs
Edge 10
'1' stop bit
UG230_c8_02_021806
UG334 (v1.0) May 28, 2007
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