Power-On Initialization; Display Configuration; Writing Data To The Display - Xilinx Spartan-3A User Manual

Chapter 5: Character LCD Screen

Power-On Initialization

The initialization sequence first establishes that the FPGA application wishes to use the
four-bit data interface to the LCD as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.

Display Configuration

After the power-on initialization is completed, the four-bit interface is established. The
next part of the sequence configures the display:
1.
2.
3.
4.

Writing Data to the Display

To write data to the display, specify the start address, followed by one or more data values.
Before writing any data, issue a
seven-bit address in the DD RAM. See
Write data to the display using a
bit data value represents the look-up address into the CG ROM or CG RAM, shown in
Figure
represent the associated character.
If the address counter is configured to auto-increment, as described earlier, the application
can sequentially write multiple character codes, and each character is automatically stored
and displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display
line. The additional characters do not automatically appear on the second line because the
DD RAM map is not consecutive from the first line to the second.
54
Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3A/3AN Starter Kit board.
Issue an Entry Mode Set command, 0x06, to set the display to automatically increment
the address pointer.
Issue a Display On/Off command, 0x0C to turn the display on and disable the cursor
and blinking.
Finally, issue a Clear Display
after issuing this command.
5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to
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command. Allow at least 1.64 ms (82,000 clock cycles)
Set DD RAM Address command to specify the initial
Figure 5-3 for DD RAM locations.
Write Data to CG RAM or DD RAM
Spartan-3A/3AN Starter Kit Board User Guide
R
command. The eight-
UG334 (v1.0) May 28, 2007