Spi Control Interface - Xilinx Spartan-3A User Manual

Chapter 9: Analog Capture Circuit
Table 9-2: Programmable Gain Settings for Pre-Amplifier (Continued)

SPI Control Interface

Figure 9-3
for each amplifier is sent as an eight-bit command word, consisting of two four-bit fields.
The most-significant bit, B3, is sent first.
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
AMP_CS
30
SPI_SCK
SPI_MOSI 7
(from FPGA)
AMP_DOUT Previous 7
(from AMP)
Figure 9-4: SPI Timing When Communicating with Amplifier
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
74
A3
Gain
B3
-5 0
-10 0
-20 0
-50 0
-100 0
highlights the SPI-based communications interface with the amplifier. The gain
AMP_DOUT
SPI_MOSI
AMP_CS
FPGA
Master
SPI_SCK
Figure 9-3: SPI Serial Interface to Amplifier
30
6 5
85 max
6
All timing is minimum in nanoseconds unless otherwise noted.
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A2 A1
B2 B1
0 1
1 0
1 0
1 1
1 1
Slave: LTC2624-1
0
A A A A
0 1 2 3
A Gain
50
4 3
5 4
Spartan-3A/3AN Starter Kit Board User Guide
A0 Input Voltage Range
B0 Minimum Maximum
1 1.4 1.9
0 1.525 1.775
1 1.5875 1.7125
0 1.625 1.675
1 1.6375 1.6625
7
B B B B
0 1 2 3
B Gain
UG334_c9_03_052407
Figure 9-4). The
50
2
3 2
UG230_c10_04_022306
UG334 (v1.0) May 28, 2007
R