Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual
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Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

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UG393 (v1.1) April 29, 2010

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  • Page 1 Spartan-6 FPGA PCB Design and Pin Planning Guide UG393 (v1.1) April 29, 2010...

  • Page 2: Revision History

    Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    Pins ........... 32 Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 4 ..........56 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 5 ......69 Recommended PCB Design Rules for BGA and CSP Packages ....70 Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 6 Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 7: Preface: About This Guide

    The provided analyses and examples can greatly accelerate the specific design. Additional Documentation The following documents are also available for downloaded at http://www.xilinx.com/support/documentation/spartan-6.htm. • Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family.

  • Page 8: Additional Support Resources

    This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs. Additional Support Resources To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support/mysupport.htm. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 9: Chapter 1: Pcb Technology Basics

    Typically, a number of planelets exist in one PCB layer. Planes and planelets distribute power to a number of points on a PCB. They are very important in the Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 10: Vias

    PCB structures described in this section (PCB Structures), both directly and indirectly. This significantly constrains the PCB designer. The www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 11: Transmission Lines

    Good signal integrity in a PCB system is dependent on having transmission lines with controlled impedance. Impedance is determined by the geometry of the traces and the Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 12: Return Currents

    They can also be a significant source of crosstalk and contributor to Power Distribution System (PDS) noise. The importance of return current paths cannot be underestimated. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 13: Chapter 2: Power Distribution System

    V capacitors are listed as the quantity per I/O bank. Device performance at full utilization is equivalent across all devices when using these recommended networks. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 14: Required Pcb Capacitor Quantities

    10 20 CSG484 LX100 13 27 CSG484 LX100T 4 13 27 CSG484 LX150 20 40 CSG484 LX150T 7 20 40 FG(G)484 LX25 FG(G)484 LX25T FG(G)484 LX45 FG(G)484 LX45T www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 15 1. PCB Capacitor specifications are listed in Table 2-2. 2. Total includes all capacitors for all supplies, accounting for the number of I/O banks in the device. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 16: Capacitor Specifications

    0.47 µF capacitor in an 0402 or 0204 package. Substitutions can be made for some characteristics, but not others; see the notes attached to Table 2-2 for details. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 17: Capacitor Consolidation Rules

    FPGA. Capacitor mounting should follow normal PCB layout practices, tending toward short and wide shapes connecting to power planes with multiple vias. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 18: 0805 Ceramic Capacitor

    (24 mils) (24 mils) (24 mils) 1.07 mm (42 mils) 1.12 mm 1.12 mm (44 mils) (44 mils) UG393_c2_01_091809 Figure 2-1: Example 0805 Capacitor Land and Mounting Geometries www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 19: 0402 Ceramic Capacitor

    These rules decrease the available options for capacitor placement but do not preclude meeting the Xilinx placement recommendations. Discuss any specific concerns with a PCB fabrication, assembly, and/or quality department.

  • Page 20: Basic Pds Principles

    This occurs on the scale of the clock frequency and the first few harmonics of the clock frequency up to about 1 GHz. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 21 PDS components: the voltage regulator, the decoupling capacitors, and the active device being powered (FPGA). X-Ref Target - Figure 2-3 DECOUPLING REGULATOR Voltage Regulator FPGA DECOUPLING UG393_c2_03_091809 Figure 2-3: Simplified PDS Circuit Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 22: Role Of Inductance

    In power system applications, the parasitic inductance (ESL) has the same or greater importance. Capacitor package dimensions (body size) determine the amount of parasitic inductance. Physically small capacitors usually have lower parasitic inductance than physically large capacitors. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 23 (ESL). These two curves combine to form the RLC circuit’s total impedance characteristic, softened or sharpened by the capacitor’s ESR. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 24: Pcb Current Path Inductance

    Figure 2-7. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 25: Plane Inductance

    The square is dimensionless; the shape of a section of a plane, not the size, determines the amount of inductance. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 26: Fpga Mounting Inductance

    Inductance is associated with any two opposing currents (for example, current flowing in a V and GND via pair). A high degree of mutual inductive coupling between www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 27: Pcb Stackup And Layer Order

    (with respect to dielectric thicknesses and etched copper areas). The PCB designer chooses the priority of the V and GND plane pairs: high priority pairs carry high transient Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 28: Capacitor Effective Frequency

    MOUNT For example, using X7R Ceramic Chip capacitor in 0402 body size: C = 0.01 μF (selected by user) = 0.9 nH (capacitor data sheet parameter) SELF www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 29 X-Ref Target - Figure 2-8 Z Value at F 2 is Equal 0805 0.47 μF 0805 Inductance (Z) 4.7 μF Inductive Portion Frequency ug393_c2_08_091809 Figure 2-8: Effective Frequency Example Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 30: Capacitor Anti-Resonance

    When the FPGA initiates a current demand change, it causes a small local disturbance in the PDS voltage (a point in the power and ground planes). To counteract this, the decoupling capacitor must first sense a voltage difference. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 31: Vref

    CCINT considered for combination, when using a 1.2V V . The supplies for the GTP transceiver pins should never be combined with other rails on the board. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 32: Unconnected Vcco Pins

    Table 2-4: EDA Tools for PDS Design and Simulation Tool Vendor Website URL Agilent http://www.agilent.com SIwave, HFSS Ansoft http://www.ansoft.com Specctraquest Power Integrity Cadence http://www.cadence.com Speed 2000, PowerSI, PowerDC, Sigrity http://www.sigrity.com OptimizePI Hyperlynx PI Mentor http://www.mentor.com www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 33: Pds Measurements

    Power system noise measurements should be made at a few different FPGA locations to ensure that any local noise phenomena are captured. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 34 In this case, the trigger was the clock for an I/O bus interface sending a 1-0-1-0 pattern at 250 Mb/s. X-Ref Target - Figure 2-9 ug393_c2_09_091809 Figure 2-9: Averaged Measurement of V Supply with Multiple I/O Sending Patterns at 250 Mb/s www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 35: Noise Spectrum Measurements

    A spectrum analyzer is a frequency-domain instrument, showing the frequency content of a voltage signal at its inputs. Using a spectrum analyzer, the user sees the exact frequencies where the PDS is inadequate. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 36 V power-supply noise, with multiple I/O sending patterns at 100 MHz. X-Ref Target - Figure 2-11 UG393_c2_11_091809 Figure 2-11: Screenshot of Spectrum Analyzer Measurement of V www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 37: Optimum Decoupling Network Design

    For inadequate connecting trace geometry and capacitor land geometry, review the loop inductance of the current path. If the vias for a decoupling capacitor are spaced a few Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 38: Possibility 3: I/O Signals In Pcb Are Stronger Than Necessary

    Restrict signals to fewer routing layers with verified continuous return current paths. • Provide low-impedance paths for AC currents to travel between reference planes (decoupling capacitors at PCB locations where layer transitions occur). www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 39: Chapter 3: Selectio Signaling

    When the voltage of the P signal is higher than the voltage of the N signal, the state is considered High. When the voltage of the N signal Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 40: Sdr Versus Ddr Interfaces

    I/Os – they must all be connected to an external reference voltage with a decoupling capacitor for each V pin. For more information on V decoupling and decoupling of all other supplies, see Chapter 2, Power Distribution System. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 41: Chapter 4: Pcb Materials And Traces

    FR4 traces can have a spread of impedance values with increasing frequency. While this spread can be insignificant at 1.125 Gb/s, it can be a concern at 10 Gb/s operation. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 42: Loss Tangent

    The impact on eye quality can be simulated to justify the use of higher cost materials. The impact of other parameters such as copper thickness can also be explored. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 43: Traces

    50Ω. To clarify, with Z at 50Ω, an even mode impedance (Z ) of 60Ω or below is desired. Figure 4-1 through Figure 4-4 show example cross sections of differential structures. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 44 Although ±10% tolerance on Z typical and can provide adequate performance, the additional cost of a tighter tolerance results in better channel performance. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 45: Trace Routing

    A plane split causes a suboptimal current return path and increases the current loop area, thereby increasing the inductance of the trace at the plane split, changing the impedance of the trace. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 46: Simulating Lossy Transmission Lines

    When selecting a cable, look for a specification of the skew between the conductors in a cable. If the conductors are not length matched, the skew appears in the common mode and directly reduces the eye height. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 47: Chapter 5: Design Of Transitions For High-Speed Signals

    TDR port. If the signal propagation speed through the transmission line is known, the location of the excess capacitance or inductance along the channel can be calculated. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 48 TDR area. X-Ref Target - Figure 5-3 Shaded area goes into the integral for Equation 13-2 UG393_c5_03_091809 Figure 5-3: Integration of Normalized TDR Area www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 49: Bga Package

    This technique allows for greater trace density than the first method, but requires 3D field-solver analysis or measurement along with several board iterations to get the desired performance. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 50 X-Ref Target - Figure 5-6 UG393_c5_06_091809 Figure 5-6: Ansoft HFSS Model of Pad Clear-Out Figure 5-7 shows the return loss comparison between 0402 pad structures with linear scale. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 51 SMT pad without the ground plane cleared from underneath. The blue curve shows that clearing out the ground plane removes much of the excess capacitance. This improvement can be quantified using Equation 5-1 Equation 5-2. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 52 5-12, clearing the ground plane under SMT pads yields a significant improvement in the performance of an SMT pad transition. Excess capacitance is reduced by 15x, and return loss is improved by 20 dB. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 53: Differential Vias

    Ground-Signal-Signal-Ground (GSSG) type differential via. Ground vias are connected to each ground plane in the stackup, while signal layers only contain pads for the entry and exit layers. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 54 For this and other configurations of differential vias, it is best to simulate a model using 3D field-solver tools to ensure that performance targets are met. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 55 For example, a shift to 34 dB return loss doubles the excess capacitance. Due to the excellent performance characteristics of GSSG vias, even long via stubs only double the differential via’s capacitance at the most. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 56: P/N Crossover Vias

    Assembly guidelines are crucial in ensuring that the process of mating the connector to the board is well-controlled to give the specified performance. Xilinx uses precision SMA connectors from Rosenberger and other precision connector manufacturers because of their excellent performance and because of the points listed in the previous paragraph.
  • Page 57 Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 58 Figure 5-17: Simulated TDR of 45 Degree Bends with Jog-Outs X-Ref Target - Figure 5-18 1E10 5E10 Frequency, Hz UG393_c5_18_091809 Figure 5-18: Simulated TDR of 45 Degree Bends with Jog-Outs www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...
  • Page 59 With Jog-outs No Jog-outs Turns & Jog-outs Turns 10 mV, 100 ps Per Div. Skew UG393_c5_20_091809 Figure 5-20: Measured TDR of 45 Degree Bends with and without Jog-Outs Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 60 Chapter 5: Design of Transitions for High-Speed Signals www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 61: Chapter 6: I/O Pin And Clock Planning

    This chapter contains guidelines for pin-planning and clocking considerations when designing with Spartan-6 FPGAs. Choosing the correct resources enables a faster and cleaner design process. Xilinx recommends using the ISE® software PlanAhead tool to select the pins for the design. Follow these guidelines to avoid board layout, pin assignment, and FPGA resource conflicts.

  • Page 62: Configuration Options

    I/O pins are usually required: RZQ and ZIO. The MIG tool adds these two additional I/O pins automatically. See the Spartan-6 FPGA Memory Controller User Guide for more information on their usage and required terminations. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 63: Mcb Clocking Considerations

    BUFIO2 Input Conflicts for SDR Data Rates and BUFIO2 Input Conflicts for DDR Data Rates tables (Chapter 1) of the Spartan-6 FPGA Clocking Resources User Guide. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 64: Gtp Transceiver Clocking Considerations

    Other GTP Transceiver Based Tools To support the desired core, and ensure enough GTP transceivers are available, use the Core Generator tool to generate valid pin placements for Xilinx provided cores. Multi-lane cores require adjacent GTP transceivers. Global and I/O Clocking Defining the best clocking structure for a design is an important aspect of pin planning.

  • Page 65: Bufio2 I/O Clock Buffer Usage

    Four I/O clocks can be driven by BUFIO2 clock buffers, each limited to that single BUFIO2 clock region. Xilinx recommends keeping the BUFIO2 driven interfaces to a single BUFIO2 clock region to conserve BUFIO2 clock buffers. Splitting a single interface across two BUFIO2 clock regions requires two BUFIO2 clock buffers;...

  • Page 66: Overview Of Bufio2 Resource Usage Per Interface Type

    The N pins can still be used for unrelated I/O, as long as they do not use a SerDes. However, these other signals must be interleaved with the SerDes bus for board routing. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning...

  • Page 67: Differential Serdes

    In addition to pin planning to avoid DRC violations, planning the pinout to optimize performance of a particular design is also important as well as considering the overall flow Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 68: Density Migration

    Chapter 7 of the Spartan-6 FPGA Packaging and Pinouts Specification provides more details on density migration. www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

  • Page 69: Appendix A: Recommended Pcb Design Rules

    Figure A-1: EIA Standard Board Layout of Soldered Pads for QFP Packages Table A-1: PCB Land Pad Dimensions for Quad Flat Pack Packages Dimension TQG144 19.80 19.80 0.50 0.3–0.4 1.60 Notes: 1. Dimensions in millimeters. Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...

  • Page 70: Recommended Pcb Design Rules For Bga And Csp Packages

    Recommended PCB Design Rules for BGA and CSP Packages Xilinx provides the diameter of a land pad on the component side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry.
  • Page 71 Via land (VL) diameter 0.51 0.27 Through hole (VH) diameter 0.25 0.15 Notes: 1. Component land pad diameter refers to the pad opening on the component side (solder mask defined). Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com UG393 (v1.1) April 29, 2010...
  • Page 72 Appendix A: Recommended PCB Design Rules www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning UG393 (v1.1) April 29, 2010...

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