Reserve Fpga V Ref Pins; Special Layout Recommendations; Related Resources - Xilinx Spartan-3A User Manual

Chapter 13: DDR2 SDRAM
Reserve FPGA V
Five pins in I/O Bank 3 are dedicated as voltage reference inputs, V
be used for general-purpose I/Os in a design. Prohibit the software from using these pins
with the constraints provided in
5i

Special Layout Recommendations

The Xilinx Memory Interface Generator (MIG) tool, version 1.7 and later, generates DDR2
SDRAM interfaces for Spartan-3A and Spartan-3AN FPGAs. The MIG implementation
leverages the FPGA's local clocking resources to capture the DDR2 SDRAM read data.
Consequently, there is a close relationship between the memory data pins (SD_DQ<15:8>,
SD_DQ_<7:0>) and their associated strobe signals. The MIG software automatically
assigns pins based on this requirement and the Spartan-3A/3AN Starter Kit board is
designed accordingly.
The MIG core for Spartan-3A/3AN FPGAs includes a loopback signal to calibrate the read
strobe timing. The loopback signal uses two FPGA pins, labeled SD_LOOP_IN and
SD_LOOP_OUT. For best performance, the length of the loop back trace must be equal to
the clock delay from the FPGA to the memory, plus the strobe delay from the memory back
to the FPGA. Put another way, the loopback trace must be one round trip time to and from
the memory. Also, the loopback signal should be in the center of the data interface pins for
best results, not near the edge or in another FPGA I/O bank. The Spartan-3A/3AN Starter
Kit board was designed accordingly.
The Xilinx Memory Interface Generator (MIG) User Guide provides additional layout
recommendations in Appendix A: "Memory Implementation Guidelines".
The board layout has been optimized for reaching frequencies above 133 MHz and
167 MHz. It can actually achieve the DDR400 performance level of 200 MHz or 400 Mbps
per I/O, with an optimized memory interface controller. It is recommended to get the
latest updates of the MIG tool that integrates the latest performance enhancements.
•
•

Related Resources

Refer to the following links for additional information:
114
Pins
REF
# Prohibit VREF pins on FPGA I/O Bank 3
CONFIG PROHIBIT = H7;
CONFIG PROHIBIT = J1;
CONFIG PROHIBIT = J8;
CONFIG PROHIBIT = L8;
CONFIG PROHIBIT = N1;
CONFIG PROHIBIT = R6;
CONFIG PROHIBIT = T1;
CONFIG PROHIBIT = T6;
Figure 13-5: UCF Location Constraints for FPGA V
Memory Interface Generator (MIG)
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
(now included with the CORE Generator™ system)
UG086: Xilinx Memory Interface Generator (MIG) User Guide
(included with MIG)
www.xilinx.com
Figure 13-5.
Spartan-3A/3AN Starter Kit Board User Guide
R
. These pins cannot
REF
Pins
REF
UG334 (v1.0) May 28, 2007