Xilinx Spartan-3A User Manual page 129

R
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
inputs, the differential input is converted to a single-ended clock signal within the
FPGA. This clock input then feeds the upper-right DCM, labeled as DCM_X2Y3.
If using for differential inputs, set the DIFF_TERM=TRUE constraint.
There are no external termination resistors provided on the board.
"Receive" Header (J2)
2
1
Bank 0
Bank 2
2
1
"Transmit" Header (J15)
Figure 15-6: Differential I/O Layout
www.xilinx.com
34
33
All traces routed with 100Ω matched impedance.
All "receive" pairs routed with matched trace lengths
within 0.25 inches.
Receive clock pair connects to global clock inputs
GCLK7 and GCLK8 that feed the top-right DCM
labeled DCM_X2Y3.
FPGA
All traces routed with 100Ω matched impedance.
All "transmit" pairs routed with matched trace lengths
within 0.25 inches.
34
33
Differential I/O Connectors
UG330_c12_15_012407
129