I 2 C Voltage Adjustment Interface; Possible Applications - Xilinx Spartan-3A User Manual

Chapter 17: Voltage Supplies
•
•
•
•
2
I C Voltage Adjustment Interface
Each LP3906 regulator has an two-wire, I
functions, such as the regulator output voltage. As indicated in
can be controlled by the FPGA application using the I/O pins indicated or by some
external controller using the through-hole mounting pads provided on the board, shown
in
Table 17-3: I

Possible Applications

For experimentation purposes only, Xilinx only recommends adjusting the two supplies
listed below:
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•
140
Caution!
If the meter offers various current ranges, always start with the largest range first.
Passing too large a current through a meter may damage it.
Reapply power to the board.
Record the current measurements across the jumper.
If the FPGA design supports the power-saving Suspend mode, measure the current
with the SUSPEND switch (see
and "SUSPEND" positions. The default FPGA application shipped with the Starter
Kit board does use the Suspend mode. For additional information on the Suspend
mode, see the "Power Management Solutions" chapter in UG331: Spartan-3 Generation
FPGA User Guide.
Convert the current measurement (Amperes or mA) to a power measurement (Watts
or mW), by multiplying the measured result by the supply voltage.
Figure 17-1.
2
C Voltage Adjustment Interface to Regulator
2
Regulator I C Control Input
IC18
IC19
By default, the V supply to the FPGA is set to 3.3V, as required for Spartan-3AN
CCAUX
FPGAs. On Spartan-3A FPGAs, V
lower power consumption at 2.5V. Consequently, V
adjusting the LDO1 output on the LP3906 regulator designated IC19. The
2
corresponding I C control signals are REG1_SCL and REG1_SDA.
By default, the reference voltage to Channels C and D on the D/A converter is 3.3V.
However, this voltage can be adjusted to between 1.0V and 3.3V by controlling the
LDO1 output on IC18. The corresponding I
REG2_SDA. See Chapter 10, "Digital-to-Analog Converter (DAC)"
information.
www.xilinx.com
"SUSPEND Switch," page
2
C serial interface that optionally controls various
FPGA Connection
REG2_SCL
SCL
(D11)
REG2_SDA
SDA
(F13)
REG1_SCL
SCL
(E13)
REG1_SDA
SDA
(D13)
can be either 2.5V or 3.3V, with potentially
CCAUX
CCAUX
2
C control signals are REG2_SCL and
Spartan-3A/3AN Starter Kit Board User Guide
26) set in both the "RUN"
2
Table 17-3, the I C interface
Through-Hole
Connection
REG2-SCL
REG2-SDA
REG1-SCL
REG1-SDA
can be reduced to 2.5V by
for additional
UG334 (v1.0) May 28, 2007
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