Digital Outputs From Analog Inputs - Xilinx Spartan-3A User Manual

Chapter 9: Analog Capture Circuit
Header J22
DAC_REF_AB
(3.3V)
DAC_REF_CD reference voltage is nominally 3.3V.
The reference is supplied by the LP3906 adjustable regulator, IC18.
DAC_REF_CD
The voltage is adjustable using the regulator's I C interface.
(3.3V)
VINA
VINB
GND
VCC
(3.3V)
FPGA
(D16) (AB14)
(T7)
(W6)
(AA20)
(W15)
(Y6)

Digital Outputs from Analog Inputs

The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in
VINA or VINB.
The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
72
LTC 6912-1 AMP
A
REF = 1.65V
SPI_MOSI
DIN 0 1 2
A GAIN
CS/LD
AMP_CS
SCK SPI Control Interface
SPI_SCK
AMP_SHDN
SHDN
AD_CONV
AMP_DOUT
AD_DOUT
Figure 9-2: Detailed View of Analog Capture Circuit
[ ]
D 13:0
=
Table 9-2.
Figure 9-2. Consequently, 1.65V is subtracted from the input voltage on
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2
B
3 0 1 2 3 DOUT
B GAIN
( )
V 1.65V
–
IN
× ×
GAIN ----------------------------------- -
1.25V
Spartan-3A/3AN Starter Kit Board User Guide
LTC 1407A-1 ADC
A/D
Channel 0
14
A/D
Channel 1
14
0 ... 13 0 ... 13
CHANNEL 1 CHANNEL 0
SCK SPI Control Interface
CONV
UG334_c9_02_052407
Equation 9-1.
8192
Equation 9-1
UG334 (v1.0) May 28, 2007
R
SDO