Transferring Eight-Bit Data Over The Four-Bit Interface; Initializing The Display - Xilinx Spartan-3A User Manual

R
Upper
4 bits
LCD_RS
LCD_DB<7:4>
LCD_RW
LCD_E
The data values on LCD_DB<7:4>, and the register select (LCD_RS) and the read/write
(LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E
goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12
or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA
generally has no reason to read information from the display.

Transferring Eight-Bit Data over the Four-Bit Interface

After initializing the display and establishing communication in four-bit mode, all
commands and data transfers to the character display are via eight bits, transferred using
two sequential four-bit operations. Each eight-bit transfer must be decomposed into two
four-bit transfers, spaced apart by at least 1 μs, as shown in
transferred first, followed by the lower nibble. An eight-bit write operation must be spaced
least 40 μs before the next communication. This delay must be increased to 1.64 ms
following a

Initializing the Display

After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient
eight-bit
available for more complex control or computation beyond simply driving the display.
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
CLOCK
LCD_RS
LCD_DB<7:4>
LCD_RW
LCD_E
Lower
4 bits
1 μs 40 μs
Figure 5-6: Character LCD Interface Timing
Clear Display command.
PicoBlaze embedded controller. After initialization, the PicoBlaze controller is
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0 = Command, 1 = Data
Valid Data
230 ns
40 ns
Figure 5-6. The upper nibble is
Operation
10 ns
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