Xilinx Spartan-3A User Manual page 111

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Table 13-1: FPGA-to-DDR2 SDRAM Connections (Continued)
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
DDR2 SDRAM
Category Signal Name
SD_DQ15
SD_DQ14
SD_DQ13
SD_DQ12
SD_DQ11
SD_DQ10
SD_DQ9
SD_DQ8
SD_DQ7
SD_DQ6
SD_DQ5
SD_DQ4
SD_DQ3
SD_DQ2
SD_DQ1
SD_DQ0
SD_BA2
SD_BA1
SD_BA0
SD_RAS
SD_CAS
SD_WE
SD_CK_N
SD_CK_P
SD_CKE
SD_CS
SD_UDM
SD_LDM
SD_UDQS_N
SD_UDQS_P
SD_LDQS_N
SD_LDQS_P
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FPGA Pin
Number
F3 Data input/output. Outputs defined for
compatibility with the Xilinx Memory
G3
Interface Generator (MIG) software.
F1
H5
H6
G1
G4
F2
H2
K4
L1
L5
L3
K1
K5
H1
P5 Bank address inputs
R3
P3
M3 Command inputs
M4
N4
M2 Differential clock input
M1
N3 Active-High clock enable input
M5 Active-Low chip select input
E3 Data Mask. Upper and Lower data masks.
J3
J5 Upper differential data strobe
K6
K2 Lower differential data strobe
K3
DDR2 SDRAM Connections
Function
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