Ucf Location Constraints; Address - Xilinx Spartan-3A User Manual

Chapter 13: DDR2 SDRAM
Table 13-1: FPGA-to-DDR2 SDRAM Connections (Continued)

UCF Location Constraints

Address

Figure 13-2
address pins, including the I/O pin assignment and the I/O standard used.
112
DDR2 SDRAM
Category Signal Name
SD_LOOP_IN
SD_LOOP_OUT
SD_ODT
provides the User Constraint File (UCF) constraints for the DDR2 SDRAM
NET "SD_A<15>" LOC
NET "SD_A<14>" LOC
NET "SD_A<13>" LOC
NET "SD_A<12>" LOC
NET "SD_A<11>" LOC
NET "SD_A<10>" LOC
NET "SD_A<9>" LOC
NET "SD_A<8>" LOC
NET "SD_A<7>" LOC
NET "SD_A<6>" LOC
NET "SD_A<5>" LOC
NET "SD_A<4>" LOC
NET "SD_A<3>" LOC
NET "SD_A<2>" LOC
NET "SD_A<1>" LOC
NET "SD_A<0>" LOC
Figure 13-2: UCF Location Constraints for DDR2 SDRAM Address Inputs
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FPGA Pin
Number
H4 I/O self-calibration loop. Direction can be
reversed if more convenient in the FPGA
H3
application.
P1 DDR2 SDRAM on-device termination control
= "W3" | IOSTANDARD = SSTL18_II ;
= "V4" | IOSTANDARD = SSTL18_II ;
= "V3" | IOSTANDARD = SSTL18_II ;
= "Y2" | IOSTANDARD = SSTL18_II ;
= "V1" | IOSTANDARD = SSTL18_II ;
= "T3" | IOSTANDARD = SSTL18_II ;
= "W2" | IOSTANDARD = SSTL18_II ;
= "W1" | IOSTANDARD = SSTL18_II ;
= "Y1" | IOSTANDARD = SSTL18_II ;
= "U1" | IOSTANDARD = SSTL18_II ;
= "U4" | IOSTANDARD = SSTL18_II ;
= "U2" | IOSTANDARD = SSTL18_II ;
= "U3" | IOSTANDARD = SSTL18_II ;
= "R1" | IOSTANDARD = SSTL18_II ;
= "T4" | IOSTANDARD = SSTL18_II ;
= "R2" | IOSTANDARD = SSTL18_II ;
Spartan-3A/3AN Starter Kit Board User Guide
Function
UG334 (v1.0) May 28, 2007
R