Xilinx Platform Flash Configuration Prom(S); Prog Push-Button Switch - Xilinx Spartan-3A User Manual

Chapter 4: FPGA Configuration Options

Xilinx Platform Flash Configuration PROM(s)

The Spartan-3A/3AN Starter Kit board includes a Xilinx Platform Flash configuration
interface. A single 4 Mbit XCF04S Platform Flash PROM appears in the JTAG chain with
the FPGA.
When using the Platform Flash PROM to configure the FPGA, the configuration mode
jumpers must be set for Master Serial mode, as shown in
configuration mode, the Platform Flash PROM must be disabled.
Table 4-2: Platform Flash Enable Jumper (J46)

PROG Push-Button Switch

The PROG push-button switch, labeled in
the configuration memory source selected by the
Press and release this button to restart the FPGA configuration process at any time.
40
Caution!
The J46 jumper, shown in
PROM on the board. Be aware of potential data contention issues with the SPI serial Flash and
the D0 line of the parallel NOR Flash, depending on the current FPGA
Jumpers", shown in Table
Caution!
If the J46 jumper shown in
FPGA's INIT_B pin controls the Platform Flash PROM's OE/RESET input. The INIT_B pin must
be High to read any data, other than from the Platform Flash PROM.
Platform Flash Platform Flash
Mode Enable (J46)
DONE
Disabled
CE
PROM
(no jumper)
GND
J46
DONE
CE
Enabled during
PROM
FPGA
GND
Configuration
J46
DONE
CE
PROM
GND
Always
J46
Enabled
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Table 4-2, page 40, enables or disables the Platform Flash
4-1.
Table 4-2, page 40
Allowed FPGA
Configuration Mode
Any
(see Table 4-1)
Master Serial
or JTAG
Master Serial
or JTAG
Figure 4-1, forces the FPGA to reconfigure from
"Configuration Mode Jumpers," page
Spartan-3A/3AN Starter Kit Board User Guide
"Configuration Mode
is set for "Always Enabled", then the
Table 4-2. If using any other
Precautions/
Contention
None. Platform Flash disabled.
The FPGA application has full
access to SPI serial Flash and
parallel NOR Flash PROMs after
configuration.
None. Platform Flash enabled
during configuration and
disabled after configuration. The
FPGA application has full access
to SPI serial Flash and parallel
NOR Flash PROMs after
configuration.
Platform Flash continuously
enabled. The FPGA application
can read additional data from
Platform Flash after
configuration as described in
application note XAPP694:
Reading User Data from
Configuration PROMs. The FPGA
application has no read access to
SPI Flash or parallel NOR Flash.
UG334 (v1.0) May 28, 2007
R
39.