Microblaze Ethernet Ip Cores - Xilinx Spartan-3A User Manual

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Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued)

MicroBlaze Ethernet IP Cores

The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an
Ethernet MAC is part of the EDK Platform Studio's Base System Builder. Both the full
Ethernet MAC and the Lite version are available for evaluation. The Ethernet Lite MAC
controller core uses fewer FPGA resources and is ideal for applications that do not require
support for interrupts, back-to-back data transfers, and statistics counters.
The Ethernet MAC core requires design constraints to meet the required performance.
Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB clock frequency
must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for
10 Mbps Ethernet operations.
The hardware evaluation versions of the Ethernet MAC cores operate for approximately
eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx
website at:
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
FPGA Pin
Signal Name
Number
E_RX_DV H10
E_RX_CLK C12
E_CRS H12
E_COL G12
E_MDC D10
E_MDIO E10
E_NRST D15
www.xilinx.com/ipcenter/processor_central/processor_ip/10-100emac/
10-100emac_order_register.htm
www.xilinx.com
Function
Receive Data Valid
Receive Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in
10Base-T mode.
Carrier Sense
MII Collision Detect
Management Clock. Serial management clock.
Management Data Input/Output
Active-Low Reset
MicroBlaze Ethernet IP Cores
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