Ucf Location Constraints - Xilinx Spartan-3A User Manual

Chapter 9: Analog Capture Circuit
ADC_OUT
AD_CONV
FPGA
Z
SPI_SCK
Master
Sample
point
AD_CONV
SPI_SCK
ADC_OUT
Figure 9-7
slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves
the ADC_OUT signal in the high-impedance state. As shown in
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
4ns min
AD_CONV
3ns
SPI_SCK
ADC_OUT

UCF Location Constraints

Figure 9-8
including the I/O pin assignment and I/O standard used.
76
D D D D D D D D D
0 1 2 3 4 5 6 7 8
Channel 1
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
Channel 0
13
Figure 9-6: Analog-to-Digital Conversion Interface
shows detailed transaction timing. The AD_CONV signal is not a traditional SPI
1 2
High-Z
AD_CONV
30
SPI_SCK
Channel 1
3 2
ADC_OUT
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
Figure 9-7: Detailed SPI Timing to ADC
provides the User Constraint File (UCF) constraints for the amplifier interface,
NET "AD_CONV" LOC = "Y6"
NET "SPI_SCK" LOC = "AA20" |
NET "AD_DOUT" LOC = "D16"
Figure 9-8: UCF Location Constraints for the ADC Interface
www.xilinx.com
Slave: LTC1407A-1 A/D Converter
D D D D D D D D
9 10 11 12 13 0 1 2
Z
Channel 1
0 13
19.6ns min
4
3 5
8ns
Channel 0
13
12
31 32
1 0
| IOSTANDARD = LVTTL |
IOSTANDARD = LVTTL |
| IOSTANDARD = LVTTL ;
Spartan-3A/3AN Starter Kit Board User Guide
D D D D D D D D D
3 4 5 6 7 8 9 10 11
Channel 0
Sample
point
0
UG334_c9_06_052407
Figure 9-6, use a 34-cycle
6
11
45ns min
33 34
6ns
High-Z
UG330_c10_06_032007
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
UG334 (v1.0) May 28, 2007
R
D D
12 13
Z
Channel 0
13
= 4 ;
= 12 ;