Intel Arria 10 User Manual page 344

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Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:
• Updated table "Arria 10 Transceiver Protocols and PHY IP Support"
— Removed SFIS and 10G SDI from the table.
— Updated Protocol Preset, Transceiver Configuration Rule, and PCS Support for protocols in the
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP section:
• Updated references of MegaWizard Plug-In Manager to IP Catalog and Parameter Editor.
• Added PCS Direct block in figure "Transceiver Native PHY IP Top Level Interfaces and Functional
Blocks".
• Updated figure "Transceiver Native PHY IP GUI" for 14.0A10 release IP GUI.
• Updated General and Datapath Parameters section
— Updated parameter descriptions in table "General and Datapath Options".
— Updated parameter descriptions in table "Transceiver Configuration Rule Parameters".
• Updated PMA Parameters section
— Updated parameter descriptions in tables "TX PMA Bonding options", "TX PLL Options", "RX PMA
— Added description for CTLE adaptation mode and updated description for DFE adaptation
• Enhanced PCS Parameters section
— Added a new table "Enhanced PCS Parameters"
— Updated the parameter descriptions in tables "Enhanced PCS TX FIFO Parameters", "Enhanced
— Added descriptions in "KR-FEC Parameters" table.
• Standard PCS Parameters
— Updated the descriptions in tables "TX and RX FIFO Parameters", "Rate Match FIFO Parameters",
• Dynamic Reconfiguration Parameters
— Removed Enable Embedded JTAG Avalon-MM Master parameter and added Altera Debug
— Added a table for "Embedded Debug Parameters".
• Updated the figure "Directory Structure for Generated Files" in IP Core File Locations section.
• Changed "one-time" to "triggered" adaptation mode for DFE and CTLE.
Made the following changes to the Interlaken section:
• Changed parameter name in the "Signals and Ports of Native PHY IP for Interlaken" figure from
tx_bonding_clock to tx_bonding_clock[5:0].
• Updated tables in the "Native PHY IP Parameter Settings for Interlaken" section:
— Added new tables: "10GBASE-R BER Checker Parameters", "KR-FEC Parameters".
— Deleted table: "Configuration Profiles Parameters".
— Added new parameters and updated existing ones to tables: "General and Datapath
— Updated existing parameters to tables: "Interlaken Frame Generator Parameters", "Interlaken
Made the following changes to the Ethernet section:
• Initial release of the XAUI PHY IP Core section.
• Changed the bus width between the FPGA fabric and PCS, and added notes 3 and 4 to the
"Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.
•
Provided the full hexadecimal values for
rx_runningdisp
• Changed the note in the Rate Match FIFO for GbE section to clarify the case where 200 ppm total is
valid.
• Added the
Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design" figure.
• Removed the Device and speed grade parameter from the "General and Datapath Options" table.
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Intel Arria 10 Transceiver PHY User Guide
344
table.
Parameters".
mode.
PCS RX FIFO Parameters", "Interlaken Frame Generator Parameters", "Interlaken Frame
Synchronizer Parameters", "10GBASE-R BER Checker Parameters", "Scrambler-Descrambler
Parameters", "Block Synchronizer Parameters", "Gearbox Parameters".
"Word Aligner and Bitslip Parameters", and "PCIe Ports".
Master Endpoint parameter and updated its description.
Parameters", "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters",
"Dynamic Reconfiguration Parameters".
CRC-32 Generator and Checker Parameters".
in the "Decoding for GbE" figure description.
circuitry, updated signals, and added a note to the "Connection
pll_cal_busy
2. Implementing Protocols in Arria 10 Transceivers
Changes
,
rx_parallel_data rx_patterndetect
UG-01143 | 2018.06.15
, and
continued...