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Parameter
PCS TX channel
bonding master
Actual PCS TX channel
bonding master
Table 12.
TX PLL Options
Parameter
TX local clock division
factor
Number of TX PLL
clock inputs per
channel
Initial TX PLL clock
input selection
Table 13.
TX PMA Optional Ports
Parameter
Enable
tx_pma_analog_reset_ack
port
Enable tx_pma_clkout port
Enable tx_pma_div_clkout
port
tx_pma_div_clkout division
factor
(24)
This clock should not be used to clock the FPGA - transceivers interface. This clock may be
used as a reference clock to an external clock cleaner.
®
®
Intel
Arria
10 Transceiver PHY User Guide
52
Value
network. The master CGB generates both the high and low speed
clocks. The master channel generates the PCS control signals and
distributes to other channels through a control plane block.
The default value is Not bonded.
Refer to Channel Bonding section in PLLs and Clock Networks
chapter for more details.
Auto, 0 to <number of
Specifies the master PCS channel for PCS bonded configurations.
channels> -1
Each Native PHY IP core instance configured with bonding must
specify a bonding master. If you select Auto, the Native PHY IP
core automatically selects a recommended channel.
The default value is Auto. Refer to the PLLs and Clock Networks
chapter for more information about the TX channel bonding
master.
0 to <number of
This parameter is automatically populated based on your selection
channels> -1
for the PCS TX channel bonding master parameter. Indicates
the selected master PCS channel for PCS bonded configurations.
Value
1, 2, 4, 8
Specifies the value of the divider available in the transceiver
channels to divide the TX PLL output clock to generate the correct
frequencies for the parallel and serial clocks.
1, 2, 3 , 4
Specifies the number of TX PLL clock inputs per channel. Use this
parameter when you plan to dynamically switch between TX PLL
clock sources. Up to four input sources are possible.
0 to <number of TX
Specifies the initially selected TX PLL clock input. This parameter
PLL clock inputs> -1
is necessary when you plan to switch between multiple TX PLL
clock inputs.
Value
On/Off
Enables the optional
This port should not be used for register mode data transfers.
On/Off
Enables the optional
speed parallel clock from the TX PMA. The source of this clock is
the serializer. It is driven by the PCS/PMA interface block.
On/Off
Enables the optional
clock is generated by the serializer. You can use this to drive core
logic, to drive the FPGA - transceivers interface.
If you select a tx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
select a tx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA high serial clock. This clock is
commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as 66:40
applications.
Disabled, 1, 2,
Selects the division factor for the
33, 40, 66
clock when enabled.
2. Implementing Protocols in Arria 10 Transceivers
Description
Description
Description
tx_pma_analog_reset_ack
output clock. This is the low
tx_pma_clkout
tx_pma_div_clkout
tx_pma_div_clkout
(25)
UG-01143 | 2018.06.15
output port.
(24)
output clock. This
output
continued...
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