Table of Contents
Advertisement
Figure 110. x4 Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 4.
®
®
Intel
Arria
10 Transceiver PHY User Guide
270
CH5
CH4
CH3
CH2
CH1
CH0
Data CH
CH5
3
Master CH
CH4
2
Data CH
1
CH3
0
CH2
Data CH
CH1
CH0
Physical
Logical
Channel
Channel
2. Implementing Protocols in Arria 10 Transceivers
fPLL
Master
ATX
CGB
PLL
Transceiver bank
fPLL
Master
ATX
CGB
PLL
fPLL
Master
ATX
CGB
PLL
Transceiver bank
fPLL
Master
ATX
CGB
PLL
UG-01143 | 2018.06.15
Hide quick links:
Advertisement
Table of Contents
