Intel Arria 10 User Manual page 474

The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done
stays high until you reset it with
•
rx_prbs_err
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
5.2.2.7. Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R
1588 protocol modes. The PRP verifier block operates in conjunction with the
descrambler. The PRP verifier monitors the output of the descrambler when block
synchronization is achieved.
The
rx_prbs_err
verifier.
The PRP verifier:
• Searches for a test pattern (two local faults, or all 0s) or its inverse
• Tracks the number of mismatches with a 16-bit error counter
Figure 247. PRP Verifier
error_count
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for
configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
® ®
Intel Arria 10 Transceiver PHY User Guide
474
—Indicates the PRBS sequence has completed one full cycle. It
rx_prbs_err_clr
—Goes high if an error occurs. This signal is pulse-extended to
—Used to reset the
error signal is shared between the PRBS checker and the PRP
Error
Counter
Test Pattern
Detect
Pseudo Random
Verifier
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
.
signal.
rx_prbs_err
Descrambler
on page 502