Intel Arria 10 User Manual page 196

2.6.4.7.6. Speed Change Summary
Table 150. Speed Change Summary
Speed Change
1GbE and 10GBASE-R
SGMII (10M, 100M and 1GbE)
1GbE, 10GBASE-R, and 10GBASE-R
with FEC
Note: You can configure the static speed while generating the IP core using the IP Parameter
Editor.
Related Information
Dynamic Reconfiguration Interface
2.6.4.8. Creating a 1G/10GbE Design
Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
1. Generate the 1G/10GbE PHY with the required parameterization.
The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the
Avalon-MM interface that you can use to read and write to PHY registers. All read
and write operations must adhere to the Avalon specification.
2. Instantiate a reset controller using the Transceiver Reset Controller Intel FPGA IP
Core in the IP Catalog. Connect the power and reset signals between the 1G/
10GbE PHY and the reset controller.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 1G/10GbE PHY
and TX PLLs. You can use any combination of fPLLs, ATX, or CMU PLLs.
4. Use the
156.25 MHz XGMII clock from the 10G reference clock.
No Memory Initialization Files (.mif) are required for the 1G/10GbE design in Arria
10 devices.
5. Complete the design by creating a top level module to connect all the IP (1G/
10GbE PHY IP, PLL IP and Reset Controller) blocks.
Related Information
• fPLL
• CMU PLL
• ATX PLL
• Using the Transceiver PHY Reset Controller
• 1G/10GbE PHY Functional Description
2.6.4.9. Design Guidelines
Consider the following guidelines while designing with 1G/10GbE PHY.
® ®
Intel Arria 10 Transceiver PHY User Guide
196
Speed Change Method
Interface Signals
Avalon-MM bus
Avalon-MM bus
from 1G/10GbE PHY or generate a fPLL to create the
tx_pma_divclk
on page 359
on page 368
on page 350
2. Implementing Protocols in Arria 10 Transceivers
• Refer to Dynamic Reconfiguration
Interface.
• Figure 77
Table 124
Table 145
on page 148
on page 433
on page 166
UG-01143 | 2018.06.15
Detailed Information
on page 197
on page 160
on page 182