Zenith Z-100 PC series Service Manual page 99

Page
4-13
Detailed Circuit Description
I nterrupt Controller
The interrupt controller (U241) prioritizes up to eight interrupt signals
to the microprocessor, stores an instruction address for each interrupt,
and generates a maskable interrupt signal (INT) for the interrupt of
highest priority. The microprocessor can tell the interrupt controller to
ignore, or mask, all interrupts, or to change the priority of the interrupts.
Maskable interrupts are acknowledged by an INTA
*
signal from the gate
array to the interrupt controller. Figure 4-7 illustrates the pinouts of the
interrupt controller.
Figure 4-7: Interrupt Controller Pinouts