Zenith Z-100 PC series Service Manual page 89

Page
4-3
Detailed Circuit Description
Table 4-1 (continued):
PIN SIGNAL
NUMBER NAME
19 CLK
20 GND
21 RESET
22 READY
23 TEST*
24
QSl
25
QSO
26 - 28
SO* - S2*
29
LOCK*
8088-2 Microprocessor Signals
DESCRIPTION
The 4.77 MHz or 8.0 MHz clock from the gate
array (U248) is connected to the 8088-2
(U235) at this pin. The clock frequency
provides the basis for all timing in the
microprocessor.
Ground for the power supply (pin 40).
This signal originates at the gate array (U248)
and causes the 8088-2 (U235) to immediately
terminate its present activity and begin the
power-up sequence.
This signal is an acknowledgment from the
addressed memory or I/O device that it will
complete the requested data transfer. The
READY signal is normally used with low­
speed devices which cannot complete a data
transfer in one bus cycle.
This signal is used only when the 8087-2
coprocessor (U234) is installed. A high state
during the "wait for test" instruction will
place the 8088-2 (U235) in an idle condition
until the 8087-2 returns the signal to a low
state.
This signal is used to communicate with the
8087-2 coprocessor (U234).
This signal is used to communicate with the
8087-2 coprocessor (U234).
These signals are decoded to prod uce the read
and write pulses for the system. Table 4-2
defines the functions of these signals.
Not connected in the Z-158.