Zenith Z-100 PC series Service Manual page 52

Page
5.3
Detailed Circuit Description
Table 5.1 (Continued). 8048/8748 Pin Definitions
DESIGNATION PIN DESCRIPTION
DBO-DB?
12-19 True bidirectional port which can be written or read synchro-
BUS
nously using the RD, WR strobes. The port also can be stati ­
cally latched. Contains the Slow order program counter dur ­
ing an external program memory fetch, and receives the ad­
dressed instruction under the control of PSEN. Also contains
the address and data during an external RAM data store
instruction, under control of ALE, RD, and WR.
TO
Input pin testable using the conditional transfer instructions
JTO and JNTO. TO can be designated as a clock output using
ENTO ClK instruction.
T1 39
Input pin testable using the JT1 and JNT1 instructions. Can
be designated the timer/counter input using the STRT CNT
instruction.
INT 6
Interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with condi­
tional jump instruction. (Active low.)
RD
S
Output strobe activated during a BUS read. Can be used
to enable data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low.)
RESET 4
Input which is used to initialize the processor. (Active low.)
WR 10 Output strobe during a bus write. (Active low.)
Used as a write strobe to external data memory.
ALE
11 Address latch enable. This signal occurs once during each
cycle. The negative edge of ALE strobes addresses into ex­
ternal data and program memory.